RPeschke

Pinned Repositories

cpp_tutorial_2021
Language:C++10
fmake
Language:Python00
ntuples
Language:C++00
Physics-Videos
Language:Python00
physwiki_py
Language:Python00
pyHDL
Converts Python script to vhdl
Language:Python30
UT4_Documentation
00
vhdl_build_system
Language:VHDL31
vhdl_csv_io
Language:VHDL20
vhdl_generic
Language:VHDL00

RPeschke's Repositories

RPeschke/pyHDL
Converts Python script to vhdl
Language:Python30
RPeschke/vhdl_build_system
Language:VHDL31
RPeschke/vhdl_csv_io
Language:VHDL20
RPeschke/cpp_tutorial_2021
Language:C++10
RPeschke/fmake
Language:Python00
RPeschke/ntuples
Language:C++00
RPeschke/Physics-Videos
Language:Python00
RPeschke/physwiki_py
Language:Python00
RPeschke/UT4_Documentation
00
RPeschke/vhdl_generic
Language:VHDL00
RPeschke/ArggLib
RPeschke/AxiStream
First Try to build an handler for axi stream
Language:VHDL
RPeschke/dataframe_helpers
Language:Python
RPeschke/example_repo
Language:VHDL
RPeschke/firmware-ethernet
Firmware modules and packages for implementing Ethernet control and data acquisition interfaces on Xilinx FPGAs.
Language:VHDL1
RPeschke/firmware-general
Generally useful firmware modules and packages, targeted for development on Xilinx FPGAs.
Language:VHDL1
RPeschke/HDPython
Language:Python
RPeschke/makeise
Simple script to automatically generate ISE project files
Language:Python
RPeschke/PyConfigFiles
Language:Python
RPeschke/python_tutorial_2021
Language:Jupyter Notebook
RPeschke/rpeschke
argg_hdl
RPeschke/SCROD_Ethernet
EthernetFirmware
Language:VHDL1
RPeschke/SCROD_ETHERNET_Example_SendBack
Language:VHDL
RPeschke/SCROD_ETHERNET_V3
Language:VHDL2
RPeschke/SCT_Correlations2
Improved version of the correlation plotting framework for SCT Test Beam DATA
Language:C++
RPeschke/SiReadFW_HMB
RPeschke/target_x_dac_control
Language:VHDL1
RPeschke/vhdl_2023
Language:C
RPeschke/vhdl_lecture
IDLAB vhdl Lecture
Language:VHDL1
RPeschke/vhdl_tutorial_2022
Language:VHDL1