Pinned Repositories
aws-fpga
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
data-parallel-CPP
Source code for 'Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL' by James Reinders, Ben Ashbaugh, James Brodman, Michael Kinsner, John Pennycook, Xinmin Tian (Apress, 2020).
DPU-PYNQ-Ultra96v2
This repository contains the procedures and files for NN model quantization and deployment with Vitis-AI on DPU-PYNQ for Ultra96v2.
ixy
A simple yet fast user space network driver for Intel 10 Gbit/s NICs written from scratch
opae-xilinx
OPAE porting to Xilinx FPGA devices.
opae-xilinx-example-afu
Example AFUs based on opae-xilinx
qemu-hdl-cosim
VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
SkyNet
virtio-fpga
A platform for emulating Virtio devices with FPGAs
virtio-fpga-bridge
Virtio front-end and back-end bridge, implemented with FPGA.
RSPwFPGAs's Repositories
RSPwFPGAs/qemu-hdl-cosim
VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
RSPwFPGAs/opae-xilinx
OPAE porting to Xilinx FPGA devices.
RSPwFPGAs/virtio-fpga-bridge
Virtio front-end and back-end bridge, implemented with FPGA.
RSPwFPGAs/virtio-fpga
A platform for emulating Virtio devices with FPGAs
RSPwFPGAs/DPU-PYNQ-Ultra96v2
This repository contains the procedures and files for NN model quantization and deployment with Vitis-AI on DPU-PYNQ for Ultra96v2.
RSPwFPGAs/data-parallel-CPP
Source code for 'Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL' by James Reinders, Ben Ashbaugh, James Brodman, Michael Kinsner, John Pennycook, Xinmin Tian (Apress, 2020).
RSPwFPGAs/ixy
A simple yet fast user space network driver for Intel 10 Gbit/s NICs written from scratch
RSPwFPGAs/opae-xilinx-example-afu
Example AFUs based on opae-xilinx
RSPwFPGAs/SkyNet
RSPwFPGAs/aws-fpga
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
RSPwFPGAs/briscv
RSPwFPGAs/CuckooHashingHLS
HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/
RSPwFPGAs/DPU-PYNQ
DPU on PYNQ
RSPwFPGAs/Edge-AI-Platform-Tutorials
Tutorials for the Edge AI Platform
RSPwFPGAs/finn
Fast, Scalable Quantized Neural Network Inference on FPGAs
RSPwFPGAs/huaweicloud-fpga
The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.
RSPwFPGAs/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
RSPwFPGAs/incubator-tvm
Open deep learning compiler stack for cpu, gpu and specialized accelerators
RSPwFPGAs/p4fpga
P4-14/16 Bluespec Compiler
RSPwFPGAs/parser-gen
Network packet parser generator
RSPwFPGAs/pcie_screamer
PCIe Screamer - TLPs experiments...
RSPwFPGAs/pcileech
Direct Memory Access (DMA) Attack Software
RSPwFPGAs/pcimem
Simple program to read & write to a pci device from userspace
RSPwFPGAs/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
RSPwFPGAs/ReActNet
ReActNet: Towards Precise Binary NeuralNetwork with Generalized Activation Functions. In ECCV 2020.
RSPwFPGAs/s6_pcie_microblaze
PCI Express DIY hacking toolkit for Xilinx SP605
RSPwFPGAs/SkrSkr
RSPwFPGAs/verilog-pcie
Verilog PCI express components
RSPwFPGAs/virtio
Virtio implementation in SystemVerilog
RSPwFPGAs/XVC_PCIe_KCU105_PR
ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.