Pinned Repositories
accelergy-timeloop-infrastructure
Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
ADaPTION
An adapted version of the original caffe deep learning library to support training, finetuning and testing of convolutional neural networks with limited numerical precision of weights and activations
AIChip
Aiming at an AI Chip based on RISC-V and NVDLA.
CaptureTheBug_RISCV_hackthon
This repo contains the materials gathered as Hackathon progress.
convnet-burden
Memory consumption and FLOP count estimates for convnets
core-v-mcu-devkit
This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.
Deep-Learning-Resources
Getting Started with Deep learning resources
dnnweaver2
Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
IterativeMAC_carnival
The project is a part of AI generated chip design contest. Designing an Iterative MAC based DNN accelerator for inference which can also train the models using same resources.
OPENROAD_FLOW_SCRIPT_IITG
It is a part of workshop organized by NINE labs at IITG for students to understand the Open Roads Flow Script (ORFS)s.
RajuMachupalli's Repositories
RajuMachupalli/IterativeMAC_carnival
The project is a part of AI generated chip design contest. Designing an Iterative MAC based DNN accelerator for inference which can also train the models using same resources.
RajuMachupalli/OPENROAD_FLOW_SCRIPT_IITG
It is a part of workshop organized by NINE labs at IITG for students to understand the Open Roads Flow Script (ORFS)s.
RajuMachupalli/accelergy-timeloop-infrastructure
Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
RajuMachupalli/ADaPTION
An adapted version of the original caffe deep learning library to support training, finetuning and testing of convolutional neural networks with limited numerical precision of weights and activations
RajuMachupalli/AIChip
Aiming at an AI Chip based on RISC-V and NVDLA.
RajuMachupalli/CaptureTheBug_RISCV_hackthon
This repo contains the materials gathered as Hackathon progress.
RajuMachupalli/convnet-burden
Memory consumption and FLOP count estimates for convnets
RajuMachupalli/core-v-mcu-devkit
This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.
RajuMachupalli/Deep-Learning-Resources
Getting Started with Deep learning resources
RajuMachupalli/dnnweaver2
Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
RajuMachupalli/hls4ml
Machine learning in FPGAs using HLS
RajuMachupalli/Image_extract
This repo is to extract contents from the input image.
RajuMachupalli/ImageNet-Datasets-Downloader
ImageNet dataset downloader. Creates a custom dataset by specifying the required number of classes and images in a class.
RajuMachupalli/linux-xlnx
The official Linux kernel from Xilinx
RajuMachupalli/lottery-ticket-hypothesis
A reimplementation of "The Lottery Ticket Hypothesis" (Frankle and Carbin) on MNIST.
RajuMachupalli/machine_learning_hardware
Paper Collection for Machine Learning Hardware
RajuMachupalli/marmot_asic
Twin SOC based on carvel and rocket-chip. a project from MPW-5 shuttels
RajuMachupalli/Neural-Networks-on-Silicon
This is a collection of works on neural networks and neural accelerators.
RajuMachupalli/Openlane_Training_VSD
As a part of open lane project training from vsdworkshop
RajuMachupalli/OpenXLA
RajuMachupalli/papers
Summaries of machine learning papers
RajuMachupalli/TCL_Workshop
TCL workshop: Learning TCL scripting through designing an UI for synthesis and timing analysis using Yosys and OpenTimer tools
RajuMachupalli/tt-fpga-hdl-demo
RajuMachupalli/tt07_iterativeMAC
implementing 32-bit MAC with 8-bit iterative multiplier for AI/ML acceleration.
RajuMachupalli/verilog_basics
Verilog basics for quick review
RajuMachupalli/VLSI-Fundamentals-A-Practical-Approach-Education-Kit
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
RajuMachupalli/vsdstdcelldesign
This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.