RajuMachupalli

RajuMachupalli's Stars

• mcbridejc/kicad_component_layout

  Scripted component layout plugin for KiCad/pcbnew

  Language:Python227

• efabless/clear

  Language:Verilog576

• esl-epfl/x-heep

  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

  Language:C14982

• TinyTapeout/caravel-mvp-pcb

  the minimum necessary to use a Caravel chip (Google MPW or chipIgnite)

  74

• stillwater-sc/RISC-V-TensorCore

  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra

  Language:Verilog4714

• pytorch/glow

  Compiler for Neural Network hardware accelerators

  Language:C++3.2k693

• LeiWang1999/ZYNQ-NVDLA

  NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

  Language:Verilog30863

• pulp-platform/ara

  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

  Language:C379133

• fengbintu/Neural-Networks-on-Silicon

  This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

  1.9k383