stillwater-sc/RISC-V-TensorCore
Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
VerilogMIT
Stargazers
- 0616yghTsinghua University
- 21st-centurymanNasdaq
- 33xsk
- ahadnagy
- aieask
- AmeyaVSBangalore, India
- damionfanUCAS
- deepsita@IIITDMKancheepuram , @SMDP-C2SD MeitY
- dimou-nikolaosHeraklion, Crete, Greece
- eda-ricercatoreDesign Automation Renegades
- FERMIWUOceanStar , Trillion Gaining, IA capital,
- gaojian16Lenovo
- HyikerBeijing University of Posts and Telecommunication
- Ihatefamous
- infini8-13IIT(BHU) Varanasi
- jgyllinsky
- kfeng123
- korallin
- KuangjuXUCAS
- lancy-xhq
- LeiWang1999Institute of Computing Technology, UCAS
- liaoyunkunInstitute of Computing Technology, Chinese Academy of Science
- luei1987kgchengdu
- lycfly
- mchtilianovSofia, Bulgaria & San Diego, California
- mfkiwl
- MrGeek-zrhUCAS
- name1e5sRight behind you!
- omasanoriJapan, or anywhere else
- RajuMachupalliUniversity of Alberta
- redlightASl
- shariethernetUnited States
- shivanishah269IIITB
- Shoadi
- stevehooverRedwood EDA (@rweda, though most of our open source work is on gitlab)
- tsgts