shariethernet

1st-CLaaS

Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

Accelerating_Standard_and_Modified_AES128

CGRA-ME

This repository contains CGRA-ME Framework from University of Toronto. This is uploaded in this repository only for quick and easy access.

Controlpath-Datapath-ASMD-DesigntoSynthesiswithSkywater130

This repository highlghts the manual design of datapath and control path with ASMD Chart and its comparison with the synthesis from behavior level RTL and finally the synthesised design is mapped to the Skywater130nm standard cells and Netlist is generated

Flight-Controller-design-for-SHAKTHI-C64-Processor

This is a SIMULINK based Control System Design for a Quadcopter. The Control System was designed in SIMULINK and the Embedded C Code and Verilog code were generated using SIMULINK Coder. This was aimed at developing a flight controller using the RISCV ISA based SHAKTHI-C64-Vajra Microprocessor developed at RISE Labs, IIT Madras, India

Infiresv0.1-RV32IC-Core

"Infires" is a series of RISC-V Cores developed using TL-Verilog. Infiresv0.1.x consists of different pipelined variants RV32I/C Cores.

Physical-Design-with-OpenLANE-using-SKY130-PDK

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified

RPHAX

RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has support for AXI-Stream IP with Single Master and Single Slave Template. The user can code the Hardware Accelerator in TL-Verilog/Verilog/System Verilog and use this flow to automatically package into an IP and create a Zynq based block design.

warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

tlvflows

shariethernet/shariethernet

shariethernet/siliconcompiler_sandpiper_saas_example

Example of using SiliconCompiler with Sandpiper-SaaS as the Frontend

shariethernet/siliconcompiler_w_sandpiper

shariethernet/warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

shariethernet/aes_adl2_fpga

shariethernet/algebraic-nnhw

AI and matrix multiplication accelerator architectures requiring half the multipliers

shariethernet/biomedbench

BiomedBench is a benchmark suite of biomedical applications targeting low-power wearables

shariethernet/caffe

Caffe: a fast open framework for deep learning.

shariethernet/cim_test_harness

shariethernet/cpu_fpga

Implement all instructions for RISC-V including Branch instructions. This repository will provide the automation flow for running the design into hardware.

shariethernet/custom_zynq_1

AXI4 Lite Slave - Zynq based Design

shariethernet/cv32e40p_viz

shariethernet/darknet_ab

YOLOv4 / Scaled-YOLOv4 / YOLO - Neural Networks for Object Detection (Windows and Linux version of Darknet )

shariethernet/edalize_18_6

An abstraction library for interfacing EDA tools

shariethernet/edalize_sandpiper_example

Example for using sandpiper with edalize front-end

shariethernet/fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

shariethernet/gf_cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

shariethernet/mltk

A Python package with command-line utilities and scripts to aid the development of machine learning models for Silicon Lab's embedded platforms

shariethernet/my_edalize

Edalize - WIP support for additional tools and flows

shariethernet/pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

shariethernet/QEMU_SystemC_app

Sample ARM application for QEMU/SystemC-based HW/SW Co-Simulation

shariethernet/Retrieval-based-Voice-Conversion-WebUI

Voice data <= 10 mins can also be used to train a good VC model!

shariethernet/riscv_myth_fpga

For use in RedwoodEDA's MYTH course

shariethernet/rtl_instr_trace_disasm

Write out the CPU instructions from the tb to a csv, then process it to get the asm

shariethernet/sauria

SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.

shariethernet/siliconcompiler

A modular build system for hardware

shariethernet/tiny_aes

shariethernet/Vitis-AI

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

shariethernet/Vitis-AI-Tutorials

shariethernet/viz_corevverif