shivanishah269

Adafruit_Python_BME280

Python Driver for the Adafruit BME280 Breakout

DSP_ActiveNoiseCancellation

Encryption_Algorithm_RSA_on_FPGA

This project is done as a part of System Design with FPGA course.

FPGA_based_Multicore_Cache_Simuator

Cache-accel: FPGA Accelerated Multi-Core Cache Simulator

mpw5_cache

mpw5_L1cache

https://caravel-user-project.readthedocs.io

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

vsdfpga

Implementation of Mixed Signal SoC (RISCV based Core + PLL) on FPGA

shivanishah269/risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

shivanishah269/FPGA_based_Multicore_Cache_Simuator

Cache-accel: FPGA Accelerated Multi-Core Cache Simulator

shivanishah269/vsdfpga

Implementation of Mixed Signal SoC (RISCV based Core + PLL) on FPGA

shivanishah269/mpw5_L1cache

https://caravel-user-project.readthedocs.io

shivanishah269/DSP_ActiveNoiseCancellation

shivanishah269/Encryption_Algorithm_RSA_on_FPGA

This project is done as a part of System Design with FPGA course.

shivanishah269/Adafruit_Python_BME280

Python Driver for the Adafruit BME280 Breakout

shivanishah269/picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

shivanishah269/mpw5_cache

shivanishah269/AOBD17_1401063

shivanishah269/gettingStartedWithGithubInIIITB

shivanishah269/StdCellLib

LibreSilicon's Standard Cell Library Generator

shivanishah269/vsdstdcelldesign

This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.