shivanishah269/risc-v-core
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
VerilogApache-2.0
Stargazers
- 00mjk
- a1waysczXin
- AI-PreeHome
- AjinkyaMahajanElectronics Engineer
- AngeloJacoboBulacan, Philippines
- Badboy1307
- BalaDhineshIndian Institute of Technology Madras
- britovski
- chiradeepdey
- combinatorylogic
- EngRaff92
- Exxcalibur
- hhutchBreezeEHR
- infini8-13IIT(BHU) Varanasi
- j23sawThane, India
- jirayupeetakul-jay
- johnjohnsonvKochi
- Kev-ranaIndia
- korallin
- mehulrijawaniHi tech engineering
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- mitoksimCalifornia
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- ninfueng@tamukohlaboratory
- OpenEDFQinan
- PatelVatsalB21
- plassaICH
- prajwaltrKarnataka, India.
- rahulrachhArizona State Univerisity
- RakshongSurattani
- romildodcm@h2o-innovation
- Sangeetha-NN
- saumilvachheta
- shivanishah269IIITB
- umenthumPortland, OR
- vineetjain07Lnmiit