RedFlag2017

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

e200_opensource

The Ultra-Low Power RISC Core

freedom

freedom-u-sdk

Freedom Unleashed Software Development Kit

mipi-csi-2

Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA

ovm_tutorial

This is a tutorial for OVM (Open Verification Methodology) testbench .

riscv-boom

BOOM: Berkeley Out-of-Order Machine

road_crack_detect

Detect crack and holes in pavement images using DeepLearning（CNN）.

rocket-soc-tb

A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs

rs-codec

Reed Solomon Encoder and Decoder Digital IP

RedFlag2017/rs-codec

Reed Solomon Encoder and Decoder Digital IP

RedFlag2017/rocket-soc-tb

A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs

RedFlag2017/freedom-u-sdk

Freedom Unleashed Software Development Kit

RedFlag2017/road_crack_detect

Detect crack and holes in pavement images using DeepLearning（CNN）.

RedFlag2017/chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

RedFlag2017/e200_opensource

The Ultra-Low Power RISC Core

RedFlag2017/freedom

RedFlag2017/mipi-csi-2

Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA

RedFlag2017/ovm_tutorial

This is a tutorial for OVM (Open Verification Methodology) testbench .

RedFlag2017/riscv-boom

BOOM: Berkeley Out-of-Order Machine

RedFlag2017/riscv-dv

SV/UVM based instruction generator for RISC-V processor verification