Reyad07

Verilog, SystemVerilog, and UVM enthusiast.

Pinned Repositories

basic_verilog
Must-have verilog systemverilog modules
Language:Verilog00
Pulp_Common_common_cells
Common SystemVerilog components forked from pulp common
Language:SystemVerilog00
common
SystemVerilog IP design & verification
Language:SystemVerilog60
risc-v-core
Language:SystemVerilog10
risc-v-model
Language:C00

Reyad07's Repositories

Reyad07/basic_verilog
Must-have verilog systemverilog modules
Language:Verilog00
Reyad07/Pulp_Common_common_cells
Common SystemVerilog components forked from pulp common
Language:SystemVerilog00