Reyad07

Reyad07's Stars

• chipsalliance/rocket-chip

  Rocket Chip Generator

  Language:Scala3.2k1.1k

• wyvernSemi/riscV

  Open source ISS and logic RISC-V 32 bit project

  Language:C++4013

• openhwgroup/core-v-verif

  Functional verification project for the CORE-V family of RISC-V cores.

  Language:Assembly444221

• openhwgroup/cvfpu

  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

  Language:SystemVerilog432115

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog958418

• alexforencich/verilog-i2c

  Verilog I2C interface for FPGA implementation

  Language:Verilog542173

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.3k687

• squared-studio/risc-v-core

  Language:SystemVerilog1

• squared-studio/common

  SystemVerilog IP design & verification

  Language:SystemVerilog6

• jerry-git/learn-python3

  Jupyter notebooks for teaching/learning Python 3

  Language:HTML6.4k1.8k

• milaan9/90_Python_Examples

  The best way to learn Python is by practicing examples. The repository contains examples of basic concepts of Python. You are advised to take the references from these examples and try them on your own.

  Language:Jupyter Notebook292228

• logisim-evolution/logisim-evolution

  Digital logic design tool and simulator

  Language:Java4.9k637

• pulp-platform/hero

  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.

  Language:SystemVerilog9424

• pulp-platform/pulpissimo

  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

  Language:SystemVerilog386167

• pulp-platform/pulp

  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

  Language:SystemVerilog450115

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.1k265

• aws/aws-fpga

  Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

  Language:VHDL1.5k516