Roa Logic BV

Pinned Repositories

adv_dbg_if
Universal Advanced JTAG Debug Interface
Language:SystemVerilog16 5 111
ahb3lite_apb_bridge
Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
Language:SystemVerilog38 5 319
ahb3lite_interconnect
AHB3-Lite Interconnect
Language:SystemVerilog78 9 426
ahb3lite_memory
Multi-Technology RAM with AHB3Lite interface
Language:SystemVerilog19 5 216
ahb3lite_pkg
Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
Language:SystemVerilog14 7 09
ahb3lite_timer
RISC-V compliant Timer IP
Language:SystemVerilog12 4 07
apb4_mux
APB4 Multiplexor
Language:SystemVerilog13 3 05
Hamming-ECC
Hamming ECC Encoder and Decoder to protect memories
Language:SystemVerilog21 3 221
plic
Platform Level Interrupt Controller
Language:SystemVerilog34 6 813
RV12
RISC-V CPU Core
Language:SystemVerilog276 20 1550

Roa Logic BV's Repositories

RoaLogic/RV12
RISC-V CPU Core
Language:SystemVerilog276 20 1550
RoaLogic/ahb3lite_interconnect
AHB3-Lite Interconnect
Language:SystemVerilog78 9 426
RoaLogic/ahb3lite_apb_bridge
Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
Language:SystemVerilog38 5 319
RoaLogic/plic
Platform Level Interrupt Controller
Language:SystemVerilog34 6 813
RoaLogic/Hamming-ECC
Hamming ECC Encoder and Decoder to protect memories
Language:SystemVerilog21 3 221
RoaLogic/ahb3lite_memory
Multi-Technology RAM with AHB3Lite interface
Language:SystemVerilog19 5 216
RoaLogic/adv_dbg_if
Universal Advanced JTAG Debug Interface
Language:SystemVerilog16 5 111
RoaLogic/ahb3lite_pkg
Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
Language:SystemVerilog14 7 09
RoaLogic/apb4_mux
APB4 Multiplexor
Language:SystemVerilog13 3 05
RoaLogic/ahb3lite_timer
RISC-V compliant Timer IP
Language:SystemVerilog12 4 07
RoaLogic/apb4_gpio
General Purpose IO with APB4 interface
Language:SystemVerilog12 3 09
RoaLogic/vga_lcd
VGA LCD Core (OpenCores)
Language:Verilog10 3 16
RoaLogic/memory
Generic memory implementations
Language:SystemVerilog9 3 212
RoaLogic/universal_jtag_tap
Universal JTAG TAP Controller
Language:SystemVerilog9 5 05
RoaLogic/vi_systemverilog_syntax
VIM Syntax file for SystemVerilog
Language:Vim script5 2 02
RoaLogic/riscv_gnu_eclipse
Eclipse Plugin for RISC-V GNU Toolchain
Language:Java4 2 34
RoaLogic/roalogic.github.io
Roa Logic GitHub Pages Site (Top Level)
Language:SCSS4 4 03
RoaLogic/adv_jtag_bridge
Language:C3 3 05
RoaLogic/apb4_uart16550
16550 UART with APB4 Interface
Language:SystemVerilog3 1 01
RoaLogic/ahb3lite_error
AHB module that always generates an error response
Language:SystemVerilog1 2 01
RoaLogic/ahb3lite_sdram_ctrl
AHB3 Lite SDRAM Controller
Language:SystemVerilog1 2 01
RoaLogic/apb_error
APB module that always generates an error response
Language:SystemVerilog1 2 01
RoaLogic/rv_soc
Roa Logic RISC-V SoC
Language:SystemVerilog1 3 01
RoaLogic/Verilator-simulation
Collection of C++ classes to create Verilator Testbenches
Language:C++1 1 0
RoaLogic/8b10b
8b10b encoder/decoder
Language:Scilab1 0
RoaLogic/OpenOCD
OpenOCD clone for porting RoaLogic Debuggers
Language:C1 02
RoaLogic/riscv-isa-manual
RISC-V Instruction Set Manual
Language:TeX
RoaLogic/rltheme
Roa Logic Theme for GitHub Pages
Language:TeX3 0
RoaLogic/rv_c_demos
C demo code to use with the rv_soc
Language:C1 0
RoaLogic/yosys
Yosys Open SYnthesis Suite
Language:C++