Issues
- 0
minstret not counting BEQ
#30 opened by elchanan36 - 2
Linux compatibility
#29 opened by JOHNTBIJU - 3
- 1
Debug Control
#28 opened by abdallah250 - 2
Synth Error: Illegal biu_size_t
#23 opened by jeppojeps - 1
casex processing
#26 opened by eshellko - 1
Design elaboration failed in Xilinx Vivado
#25 opened by kshitij-r - 7
- 0
- 0
can't run simulation with vcs
#22 opened by mancomao - 2
- 1
can't run simulation with iverilog
#15 opened by frantony - 5
Documents Update
#9 opened by riscveval - 1
about the core simulation
#18 opened by youping2009 - 1
Reading MCYCLE causes trap
#19 opened by drichmond