can't run simulation with iverilog
frantony opened this issue · 1 comments
frantony commented
I can't find documentation on running RV12 simulation with Icarus Verilog.
I can only guess how to run iverilog simulation.
Here is my command secuence under Debian Linux:
$ iverilog -v
Icarus Verilog version 10.1 (stable) ()
...
$ git clone --recursive https://github.com/RoaLogic/RV12
$ cd RV12
RV12 $ make -C sim/ahb3lite/regression/bin SIMULATORS=icarus TECHNOLOGY=generic icarus
Here is output error log:
make: Entering directory '/home/antony/RV12/sim/ahb3lite/regression/bin'
make[1]: Entering directory '/home/antony/RV12/sim/ahb3lite/regression/bin/icarus'
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:125: syntax error
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:125: error: invalid module item.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:126: error: port HSEL is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:127: error: port HADDR is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:128: error: port HWDATA is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:129: error: port HRDATA is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:130: error: port HWRITE is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:131: error: port HSIZE is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:132: error: port HBURST is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:133: error: port HPROT is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:134: error: port HTRANS is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:135: error: port HMASTLOCK is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:136: error: port HREADY is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:137: error: port HRESP is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:138: syntax error
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:143: error: invalid module item.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:146: syntax error
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:146: error: invalid module item.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:147: error: port HSEL is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:109: error: Port ``HSEL'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:148: error: port HADDR is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:110: error: Port ``HADDR'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:149: error: port HWDATA is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:111: error: Port ``HWDATA'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:150: error: port HRDATA is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:112: error: Port ``HRDATA'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:151: error: port HWRITE is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:113: error: Port ``HWRITE'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:152: error: port HSIZE is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:114: error: Port ``HSIZE'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:153: error: port HBURST is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:115: error: Port ``HBURST'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:154: error: port HPROT is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:116: error: Port ``HPROT'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:155: error: port HTRANS is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:117: error: Port ``HTRANS'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:156: error: port HMASTLOCK is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:118: error: Port ``HMASTLOCK'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:157: error: port HREADY is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:119: error: Port ``HREADY'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:158: error: port HREADYOUT is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:159: error: port HRESP is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:121: error: Port ``HRESP'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:160: syntax error
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:165: error: invalid module item.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:242: sorry: modport task/function ports are not yet supported.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:292: warning: task definition for "set_not_ready" has an empty port declaration list!
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:298: warning: task definition for "set_ready" has an empty port declaration list!
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:304: warning: task definition for "set_error" has an empty port declaration list!
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:245: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:248: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:249: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:249: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:252: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:253: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:253: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:256: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:257: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:257: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:260: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:261: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:261: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:264: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:265: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:265: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:268: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:269: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:269: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:272: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:273: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:273: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:75: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:82: error: duplicate definition for localparam 'SBITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:84: error: duplicate declaration for net or variable 'opcode' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:85: error: duplicate declaration for net or variable 'func3' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:86: error: duplicate declaration for net or variable 'func7' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:87: error: duplicate declaration for net or variable 'is_rv64' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:179: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:182: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:183: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:183: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:184: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:184: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:185: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:186: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:187: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:193: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:194: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:194: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:195: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:195: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:196: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:196: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:197: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:197: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:198: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:198: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:199: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:199: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:200: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:200: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:201: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:201: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:202: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:202: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:203: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:203: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:204: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:204: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:205: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:211: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:212: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:212: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:213: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:221: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:222: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:222: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:223: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:223: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:224: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:224: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:225: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:225: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:226: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:226: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:227: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:227: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:228: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:228: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:229: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:229: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:230: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:230: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:231: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:231: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:232: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:232: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:233: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:238: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:239: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:239: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:240: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:240: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:241: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:241: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:242: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:242: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:243: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:249: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:250: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:250: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:251: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:251: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:252: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:252: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:253: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:253: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:254: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:254: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:255: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:255: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:256: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:256: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:257: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:257: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:258: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:263: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:264: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:264: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:265: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:265: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:266: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:266: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:267: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:277: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:288: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:290: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:291: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:291: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:292: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:292: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:293: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:293: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:294: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:294: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:295: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:295: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:296: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:296: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:297: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:297: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:298: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:302: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:306: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:308: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:309: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:309: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:310: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:310: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:311: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:311: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:312: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:312: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:313: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:313: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:314: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:319: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:342: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:85: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:177: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:180: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:181: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:181: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:182: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:183: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:184: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:187: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:188: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:188: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:189: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:190: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:191: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:194: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:195: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:195: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:196: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:197: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:198: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:201: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:202: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:202: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:203: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:204: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:205: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:208: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:209: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:209: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:210: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:211: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:212: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:215: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:216: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:216: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:217: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:218: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:219: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:222: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:223: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:223: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:224: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:225: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:226: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:229: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:230: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:230: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:231: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:232: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:233: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:237: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:238: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:238: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:239: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:240: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:241: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:244: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:245: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:245: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:246: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:247: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:248: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:252: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:253: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:253: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:254: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:255: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:256: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:268: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:269: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:269: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:270: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:272: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:273: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:274: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:275: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:279: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:280: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:280: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:281: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:283: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:284: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:285: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:289: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:290: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:290: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:291: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:293: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:294: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:295: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:297: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:297: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:301: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:303: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:60: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:78: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:79: error: malformed statement
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:87: error: duplicate definition for function 'sext32' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:123: error: duplicate declaration for net or variable 'opcode' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:124: error: duplicate declaration for net or variable 'func3' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:125: error: duplicate declaration for net or variable 'func7' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:129: error: duplicate declaration for net or variable 'opA32' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:130: error: duplicate declaration for net or variable 'opB32' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:142: error: duplicate declaration for net or variable 'state' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:180: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:182: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:183: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:183: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:184: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:184: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:185: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:190: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:191: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:191: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:192: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:192: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:193: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:193: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:194: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:199: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:200: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:200: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:201: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:201: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:202: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:202: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:203: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:203: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:204: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:204: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:205: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:209: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:297: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:298: Syntax in assignment statement l-value.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:299: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:299: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:300: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:300: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:301: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:309: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:310: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:310: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:311: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:311: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:312: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:312: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:313: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:313: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:314: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:314: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:315: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:321: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:322: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:322: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:324: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:325: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:329: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:331: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:337: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:338: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:338: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:342: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:343: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:343: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:345: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:346: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:351: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:352: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:354: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:355: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:355: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:357: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:358: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:61: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:66: error: duplicate definition for function 'sext32' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:75: error: duplicate definition for function 'twos' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:82: error: duplicate definition for function 'abs' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:96: error: duplicate declaration for net or variable 'opcode' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:97: error: duplicate declaration for net or variable 'func3' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:98: error: duplicate declaration for net or variable 'func7' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:99: error: duplicate declaration for net or variable 'is_rv64' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:102: error: duplicate declaration for net or variable 'opA32' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:103: error: duplicate declaration for net or variable 'opB32' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:105: error: duplicate declaration for net or variable 'cnt' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:121: error: duplicate declaration for net or variable 'state' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:197: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:200: Syntax in assignment statement l-value.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:201: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:223: error: Incomprehensible case expression.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:380: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:381: Syntax in assignment statement l-value.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:400: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:401: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:402: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:402: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:403: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:406: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:407: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:407: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:408: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:408: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:409: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:409: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:410: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:410: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:411: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:411: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:412: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:412: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:413: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:413: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:414: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:414: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:415: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:126: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:137: error: duplicate declaration for net or variable 'alu_r' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:143: error: duplicate declaration for net or variable 'alu_bubble' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:189: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:191: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:192: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:192: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:193: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:193: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:194: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:194: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:195: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:199: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:200: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:200: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:201: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:201: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:202: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:202: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:203: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:214: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:277: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:279: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:280: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:280: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:281: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:281: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:282: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:282: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:283: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:290: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:292: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:292: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:293: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:294: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:295: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:112: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:131: error: duplicate declaration for net or variable 'ex_opcode' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:137: error: duplicate declaration for net or variable 'is_rv64' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:268: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:271: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:272: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:272: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:273: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:273: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:274: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:274: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:275: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:275: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:276: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:276: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:277: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:277: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:278: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:278: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:279: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:279: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:280: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:280: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:281: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:281: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:282: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:282: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:283: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:291: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:292: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:292: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:295: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:296: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:296: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:299: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:300: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:300: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:303: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:304: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:304: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:307: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:308: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:308: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:311: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:312: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:312: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:315: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:316: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:316: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:319: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:320: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:320: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:323: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:324: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:324: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:327: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:328: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:328: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:331: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:332: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:332: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:335: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:336: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:336: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:346: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:347: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:347: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:348: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:349: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:350: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:350: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:353: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:354: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:354: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:357: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:358: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:358: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:361: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:362: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:362: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:365: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:366: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:366: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:368: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:369: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:369: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:370: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:371: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:372: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:372: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:375: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:376: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:376: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:379: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:380: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:380: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:382: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:383: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:383: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:384: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:384: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:385: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:385: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:386: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:386: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:387: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:388: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:389: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:389: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:392: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:393: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:393: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:396: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:397: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:397: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:400: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:401: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:401: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:413: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:414: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:414: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:415: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:415: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:416: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:416: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:417: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:417: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:418: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:418: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:419: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:419: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:420: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:420: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:421: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:421: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:422: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:422: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:423: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:423: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:424: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:424: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:425: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:430: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:431: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:431: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:432: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:432: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:433: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:433: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:434: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:434: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:435: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:435: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:436: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:436: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:437: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:437: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:438: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:438: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:439: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:439: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:440: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:440: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:441: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:441: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:442: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:455: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:456: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:456: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:458: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:459: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:462: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:463: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:463: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:465: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:466: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:469: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:470: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:470: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:472: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:473: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:476: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:477: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:477: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:479: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:480: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:483: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:484: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:484: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:486: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:487: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:490: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:491: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:491: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:493: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:494: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:497: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:498: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:498: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:500: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:501: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:504: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:505: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:505: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:507: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:508: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:511: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:512: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:512: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:514: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:515: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:518: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:519: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:519: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:521: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:522: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:531: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:532: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:532: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:548: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:548: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:555: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:557: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:558: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:558: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:559: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:559: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:560: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:566: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:567: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:567: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:568: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:568: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:569: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:569: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:570: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:570: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:571: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:571: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:572: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:572: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:573: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:573: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:574: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:577: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:578: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:578: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:579: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:579: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:580: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:580: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:581: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:581: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:582: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:582: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:583: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:583: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:584: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:584: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:585: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:585: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:586: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:586: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:587: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:587: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:588: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:588: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:589: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:589: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:590: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:590: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:591: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:591: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:592: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:592: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:593: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:593: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:594: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:594: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:595: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:595: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:596: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:596: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:597: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:597: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:598: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:598: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:599: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:599: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:600: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:600: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:601: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:601: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:602: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:602: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:603: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:603: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:604: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:604: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:605: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:605: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:606: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:606: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:607: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:607: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:608: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:608: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:609: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:609: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:610: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:610: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:611: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:611: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:612: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:612: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:613: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:613: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:614: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:614: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:617: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:617: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:618: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:618: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:619: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:619: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:620: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:620: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:621: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:621: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:622: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:622: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:624: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:624: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:625: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:631: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:632: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:632: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:633: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:633: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:634: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:634: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:635: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:635: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:636: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:636: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:637: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:637: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:638: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:638: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:639: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:639: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:640: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:640: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:641: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:641: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:644: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:644: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:645: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:651: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:652: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:652: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:653: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:653: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:654: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:654: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:655: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:655: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:656: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:656: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:657: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:657: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:658: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:658: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:659: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:659: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:660: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:660: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:661: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:661: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:662: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:662: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:663: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:663: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:664: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:664: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:665: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:673: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:674: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:674: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:675: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:675: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:676: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:676: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:677: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:677: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:678: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:678: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:679: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:679: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:680: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:680: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:681: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:681: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:682: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:682: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:683: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:683: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:684: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:684: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:685: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:685: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:686: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:686: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:688: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:688: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:689: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:689: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:690: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:690: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:692: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:692: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:693: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:693: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:694: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:694: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:695: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:695: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:696: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:696: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:697: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:697: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:698: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:698: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:699: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:699: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:700: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:700: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:701: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:701: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:702: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:702: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:704: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:704: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:705: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:705: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:706: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:706: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:707: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:707: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:708: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:708: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:709: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:709: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:710: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:710: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:711: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:711: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:712: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:712: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:713: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:713: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:715: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:715: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:716: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:716: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:717: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:717: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:718: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:718: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:719: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:719: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:720: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:720: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:721: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:721: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:722: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:722: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:723: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:723: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:724: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:724: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:725: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:725: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:726: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:726: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:727: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:727: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:728: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:728: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:729: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:729: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:730: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:730: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:731: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:731: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:732: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:732: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:733: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:733: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:734: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:734: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:735: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:735: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:737: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:737: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:738: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:742: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:743: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:743: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:744: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:744: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:745: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:745: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:746: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:746: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:747: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:747: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:748: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:748: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:749: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:749: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:750: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:750: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:751: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:751: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:752: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:752: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:753: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:753: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:754: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:754: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:755: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:755: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:757: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:757: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:758: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:758: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:759: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:759: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:761: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:761: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:762: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:762: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:763: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:763: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:764: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:764: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:765: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:765: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:766: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:766: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:767: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:767: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:768: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:768: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:769: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:769: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:770: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:770: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:771: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:771: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:773: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:773: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:774: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:774: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:775: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:775: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:776: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:776: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:777: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:777: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:778: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:778: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:779: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:779: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:780: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:780: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:781: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:781: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:782: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:782: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:784: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:784: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:785: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:785: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:786: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:786: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:787: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:787: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:788: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:788: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:789: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:789: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:790: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:790: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:791: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:791: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:792: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:792: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:793: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:793: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:794: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:794: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:795: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:795: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:796: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:796: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:797: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:797: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:798: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:798: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:799: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:799: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:800: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:800: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:801: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:801: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:802: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:802: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:803: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:803: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:804: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:804: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:805: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:805: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:806: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:806: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:807: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:807: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:809: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:809: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:810: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:810: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:812: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:812: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:813: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:78: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:106: error: duplicate declaration for net or variable 'opcode' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:219: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:221: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:222: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:222: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:223: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:223: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:224: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:228: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:229: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:229: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:230: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:230: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:249: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:253: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:254: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:254: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:259: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:260: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:260: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:263: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:264: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:264: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:269: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:270: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:270: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:303: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:70: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:77: error: duplicate declaration for net or variable 'opcode' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:78: error: duplicate declaration for net or variable 'func3' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:79: error: duplicate declaration for net or variable 'func7' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:83: error: duplicate declaration for net or variable 'mem_data' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:84: error: duplicate declaration for net or variable 'mem_qb' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:85: error: duplicate declaration for net or variable 'mem_qh' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:86: error: duplicate declaration for net or variable 'mem_qw' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:184: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_rf.sv:68: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_rf.sv:126: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:117: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:222: error: duplicate declaration for net or variable 'is_rv64' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:223: error: duplicate declaration for net or variable 'has_rvc' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:227: error: duplicate declaration for net or variable 'has_muldiv' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:228: error: duplicate declaration for net or variable 'has_amo' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:291: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:298: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:299: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:299: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:300: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:300: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:301: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:301: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:302: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:302: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:303: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:303: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:304: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:304: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:305: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:305: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:307: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:307: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:308: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:308: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:309: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:309: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:310: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:310: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:311: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:311: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:312: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:312: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:313: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:313: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:314: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:314: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:315: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:315: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:318: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:331: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:332: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:332: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:333: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:333: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:334: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:334: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:335: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:335: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:336: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:336: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:337: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:337: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:338: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:338: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:339: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:339: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:340: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:340: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:341: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:341: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:344: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:360: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:361: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:361: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:362: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:362: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:363: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:363: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:364: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:364: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:365: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:365: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:366: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:366: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:367: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:367: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:368: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:368: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:369: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:369: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:372: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:372: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:373: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:373: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:374: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:374: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:375: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:375: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:376: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:376: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:377: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:396: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:397: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:397: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:398: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:398: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:399: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:399: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:400: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:400: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:401: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:401: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:402: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:402: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:403: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:403: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:404: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:404: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:405: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:405: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:406: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:406: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:407: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:407: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:408: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:408: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:409: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:409: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:410: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:410: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:411: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:411: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:412: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:412: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:413: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:413: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:414: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:414: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:415: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:415: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:416: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:416: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:418: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:418: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:419: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:425: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:426: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:426: error: syntax error in continuous assignment
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:900: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:902: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:903: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:903: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:904: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:904: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:905: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:905: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:906: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:906: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:907: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:907: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:908: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:908: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:909: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:909: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:910: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:910: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:911: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:911: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:912: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:912: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:913: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:913: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:914: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:914: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:915: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:920: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:937: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:939: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:940: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:940: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:941: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:941: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:942: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:942: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:943: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:943: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:944: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:944: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:945: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:945: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:946: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:946: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:947: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:947: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:948: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:948: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:949: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:949: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:950: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:950: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:951: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:951: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:952: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:954: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:1280: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_bp.sv:67: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_bp.sv:141: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:94: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:229: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:231: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:232: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:232: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:233: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:233: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:234: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:234: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:236: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:236: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:237: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:237: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:239: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:239: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:240: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:240: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:242: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:242: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:243: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:243: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:245: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:245: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:246: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:246: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:248: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:248: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:249: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:249: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:251: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:251: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:252: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:252: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:254: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:254: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:255: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:255: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:257: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:257: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:258: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:258: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:260: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:260: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:261: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:265: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:266: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:266: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:267: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:267: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:268: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:268: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:269: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:269: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:270: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:270: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:271: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:271: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:272: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:283: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:284: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:284: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:288: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:289: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:289: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:297: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:298: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:298: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:302: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:303: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:303: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:307: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:308: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:308: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:312: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:312: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:312: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:312: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:319: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:320: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:320: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:321: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:323: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:325: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:331: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:332: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:332: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:391: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:396: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:413: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:416: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:417: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:430: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:438: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:445: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:446: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:448: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:449: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:449: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:450: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:450: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:451: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:451: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:457: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:457: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:458: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:463: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:464: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:124: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:149: error: duplicate declaration for net or variable 'ex_bubble' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:154: error: duplicate declaration for net or variable 'du_flush' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:158: error: duplicate declaration for net or variable 'wb_stall' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:159: error: duplicate declaration for net or variable 'du_stall' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:170: error: duplicate declaration for net or variable 'bu_bp_update' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:194: error: duplicate declaration for net or variable 'ex_memadr' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:206: error: duplicate declaration for net or variable 'ex_csr_reg' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:207: error: duplicate declaration for net or variable 'ex_csr_wval' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:209: error: duplicate declaration for net or variable 'ex_csr_we' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:212: error: duplicate declaration for net or variable 'wb_dst' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:224: error: duplicate declaration for net or variable 'du_dati_rf' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:227: error: duplicate declaration for net or variable 'du_ie' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:228: error: duplicate declaration for net or variable 'du_exceptions' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:394: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w.sv:64: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w.sv:141: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:62: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:68: error: genvar 'i' has already been declared.
/home/antony/RV12/rtl/verilog/core/riscv_rf.sv:85: the previous declaration is here.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:82: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:87: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:88: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:92: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:93: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:102: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:103: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:63: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:66: error: genvar 'i' has already been declared.
/home/antony/RV12/rtl/verilog/core/riscv_rf.sv:85: the previous declaration is here.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:70: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:72: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:73: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:107: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:108: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:63: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:69: error: duplicate declaration for net or variable 'biten' in 'riscv_alu'.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:70: error: genvar 'i' has already been declared.
/home/antony/RV12/rtl/verilog/core/riscv_rf.sv:85: the previous declaration is here.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:73: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:75: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:76: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:129: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:130: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:162: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:163: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw.sv:59: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw.sv:92: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:58: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:64: error: genvar 'i' has already been declared.
/home/antony/RV12/rtl/verilog/core/riscv_rf.sv:85: the previous declaration is here.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:66: error: duplicate declaration for net or variable 'mem_array' in 'riscv_alu'.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:77: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:82: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:83: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:87: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:88: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:95: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:96: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_easic_n3x.sv:58: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_easic_n3x.sv:80: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:53: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:60: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:62: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:63: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:63: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:64: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:64: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:65: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:65: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:66: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:66: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:67: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:67: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:68: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:68: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:69: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:69: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:70: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:75: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:76: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:76: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:77: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:77: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:78: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:78: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:79: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:79: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:80: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:80: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:81: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:81: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:82: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:82: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:83: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:83: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:84: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:84: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:85: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:85: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:86: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:86: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:87: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:87: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:88: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:88: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:89: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:89: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:90: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:90: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:91: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:96: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:97: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:97: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:98: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_wbuf.sv:68: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_wbuf.sv:243: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:87: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:151: error: Typedef identifier "fifo_struct" is already a type name.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:158: error: genvar 'way' has already been declared.
/home/antony/RV12/rtl/verilog/core/riscv_wbuf.sv:101: the previous declaration is here.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:198: error: duplicate declaration for net or variable 'cnt' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:246: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:263: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:291: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:297: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:389: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:392: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:393: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:394: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:395: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:401: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:401: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:401: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:401: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:406: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:407: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:408: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:411: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:416: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:423: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:425: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:426: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:426: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:427: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:427: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:428: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:430: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:455: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:459: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:462: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:465: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:468: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:472: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:479: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:493: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:494: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:494: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:496: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:498: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:500: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:505: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:506: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:506: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:508: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:510: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:511: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:515: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:517: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:517: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:518: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:519: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:520: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:524: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:525: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:525: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:526: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:527: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:528: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:534: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:535: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:535: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:564: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:565: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:566: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:568: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:569: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:569: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:570: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:570: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:571: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:574: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:699: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:77: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:100: error: Typedef identifier "fifo_struct" is already a type name.
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:107: error: duplicate declaration for net or variable 'is_cacheable' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:109: error: duplicate declaration for net or variable 'biu_stb_cnt' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:110: error: duplicate declaration for net or variable 'biu_fifo' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:111: error: duplicate declaration for net or variable 'if_flush_dly' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:284: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:87: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:92: error: duplicate definition for localparam 'SETS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:93: error: duplicate definition for localparam 'BLK_OFF_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:94: error: duplicate definition for localparam 'IDX_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:95: error: duplicate definition for localparam 'TAG_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:96: error: duplicate definition for localparam 'LRU_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:97: error: duplicate definition for localparam 'BLK_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:98: error: duplicate definition for localparam 'BURST_SIZE' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:99: error: duplicate definition for localparam 'BURST_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:100: error: duplicate definition for localparam 'BURST_OFF' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:101: error: duplicate definition for localparam 'BURST_LSB' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:104: error: duplicate definition for localparam 'DAT_ABITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:105: error: duplicate definition for localparam 'DAT_IDX_LSB' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:106: error: duplicate definition for localparam 'DAT_IDX_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:117: error: duplicate definition for function 'onehot2int' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:127: error: duplicate definition for function 'new_lru' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:157: error: Typedef identifier "tag_struct" is already a type name.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:158: error: duplicate definition for localparam 'TAG_STRUCT_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:165: error: genvar 'way' has already been declared.
/home/antony/RV12/rtl/verilog/core/riscv_wbuf.sv:101: the previous declaration is here.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:166: error: duplicate declaration for net or variable 'n' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:171: error: duplicate declaration for net or variable 'is_cacheable' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:190: error: duplicate declaration for net or variable 'tag_widx' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:192: error: duplicate declaration for net or variable 'dat_widx' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:193: error: duplicate declaration for net or variable 'core_tag' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:196: error: duplicate declaration for net or variable 'way_hit' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:199: error: duplicate declaration for net or variable 'way_dat' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:200: error: duplicate declaration for net or variable 'tag_re' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:201: error: duplicate declaration for net or variable 'tag_we' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:202: error: duplicate declaration for net or variable 'dat_we' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:203: error: duplicate declaration for net or variable 'dat_in' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:204: error: duplicate declaration for net or variable 'dat_out' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:205: error: duplicate declaration for net or variable 'dat_be' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:206: error: duplicate declaration for net or variable 'tag_in' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:207: error: duplicate declaration for net or variable 'tag_out' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:214: error: duplicate declaration for net or variable 'cache_hit' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:215: error: duplicate declaration for net or variable 'dcache_hit' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:217: error: duplicate declaration for net or variable 'cache_dat' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:220: error: duplicate declaration for net or variable 'way_random' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:221: error: duplicate declaration for net or variable 'fill_way_select' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:222: error: duplicate declaration for net or variable 'fill_way_select_rnd' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:224: error: duplicate declaration for net or variable 'state' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:225: error: duplicate declaration for net or variable 'hold_bu_cacheflush' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:226: error: duplicate declaration for net or variable 'flushing' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:227: error: duplicate declaration for net or variable 'filling' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:230: error: duplicate declaration for net or variable 'cnt' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:230: error: duplicate declaration for net or variable 'nxt_cnt' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:300: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:317: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:347: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:353: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:595: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:598: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:599: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:600: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:601: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:606: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:615: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:620: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:621: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:627: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:640: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:643: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:644: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:645: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:646: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:647: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:648: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:648: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:649: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:649: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:650: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:650: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:651: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:651: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:652: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:652: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:653: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:653: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:654: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:658: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:661: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:663: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:664: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:664: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:665: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:675: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:682: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:684: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:685: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:687: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:688: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:688: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:689: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:689: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:690: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:690: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:691: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:691: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:692: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:693: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:694: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:694: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:695: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:700: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:701: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:701: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:702: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:702: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:703: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:703: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:704: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:704: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:705: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:709: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:721: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:727: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:728: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:729: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:730: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:731: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:732: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:736: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:736: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:736: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:736: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:744: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:747: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:753: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:757: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:764: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:776: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:777: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:778: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:779: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:779: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:780: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:780: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:781: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:786: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:787: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:787: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:788: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:788: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:789: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:789: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:790: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:790: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:792: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:792: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:793: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:793: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:794: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:798: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:799: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:799: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:828: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:830: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:831: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:831: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:832: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:832: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:833: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:833: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:834: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:838: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:884: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:892: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:893: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:893: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:894: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:898: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:899: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:899: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:900: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:905: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:906: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:906: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:908: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:914: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:915: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:915: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:916: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:920: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:921: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:921: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:923: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:928: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:929: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:929: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:930: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:935: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:936: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:936: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:937: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:943: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:944: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:944: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:946: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:951: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:952: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:952: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:953: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:957: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:958: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:958: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:959: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1034: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1035: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1037: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1038: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1038: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1039: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1039: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1040: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1045: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1045: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1045: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1045: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1047: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1048: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1049: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1049: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1049: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1049: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1052: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1054: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1055: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1059: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1060: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1062: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1063: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1063: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1064: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1064: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1065: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1068: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1069: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1071: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1072: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1072: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1073: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1073: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1074: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1080: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1085: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1089: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1090: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1090: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1094: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1095: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1095: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1099: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1100: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1100: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1104: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1105: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1105: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1109: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1110: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1110: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1115: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1116: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1116: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1120: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1121: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1121: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1125: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1126: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1126: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1130: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1131: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1131: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1135: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1136: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1136: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1144: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1152: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1157: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1158: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1160: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1161: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1161: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1162: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1162: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1163: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:77: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:89: error: duplicate declaration for net or variable 'state' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:91: error: duplicate declaration for net or variable 'is_cacheable' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:213: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:215: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:216: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:216: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:217: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:217: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:218: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:218: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:219: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:221: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:234: syntax error
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_cache_biu_ahb3lite.sv:78: error: invalid module item.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_cache_biu_ahb3lite.sv:278: syntax error
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:87: error: invalid module item.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:101: error: duplicate declaration for net or variable 'biu_stb' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:102: error: duplicate declaration for net or variable 'biu_stb_ack' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:104: error: duplicate declaration for net or variable 'biu_adri' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:105: error: duplicate declaration for net or variable 'biu_be' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:106: error: duplicate declaration for net or variable 'biu_type' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:107: error: duplicate declaration for net or variable 'biu_lock' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:108: error: duplicate declaration for net or variable 'biu_we' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:109: error: duplicate declaration for net or variable 'biu_di' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:110: error: duplicate declaration for net or variable 'biu_do' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:111: error: duplicate declaration for net or variable 'biu_rack' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:114: error: duplicate declaration for net or variable 'biu_is_cacheable' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:115: error: duplicate declaration for net or variable 'biu_is_instruction' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:116: error: duplicate declaration for net or variable 'biu_prv' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:189: syntax error
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:87: error: invalid module item.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:105: error: duplicate declaration for net or variable 'cache_req' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:107: error: duplicate declaration for net or variable 'cache_adr' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:108: error: duplicate declaration for net or variable 'cache_we' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:109: error: duplicate declaration for net or variable 'cache_d' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:111: error: duplicate declaration for net or variable 'cache_be' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:112: error: duplicate declaration for net or variable 'cache_prv' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:113: error: duplicate declaration for net or variable 'cache_flush' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:116: error: duplicate declaration for net or variable 'biu_stb' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:117: error: duplicate declaration for net or variable 'biu_stb_ack' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:118: error: duplicate declaration for net or variable 'biu_adro' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:119: error: duplicate declaration for net or variable 'biu_adri' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:120: error: duplicate declaration for net or variable 'biu_be' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:121: error: duplicate declaration for net or variable 'biu_type' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:122: error: duplicate declaration for net or variable 'biu_lock' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:123: error: duplicate declaration for net or variable 'biu_we' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:124: error: duplicate declaration for net or variable 'biu_di' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:125: error: duplicate declaration for net or variable 'biu_do' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:126: error: duplicate declaration for net or variable 'biu_wack' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:127: error: duplicate declaration for net or variable 'biu_rack' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:128: error: duplicate declaration for net or variable 'biu_err' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:130: error: duplicate declaration for net or variable 'biu_is_cacheable' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:131: error: duplicate declaration for net or variable 'biu_is_instruction' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:132: error: duplicate declaration for net or variable 'biu_prv' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:286: syntax error
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:73: warning: extra digits given for sized hex constant.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:74: warning: extra digits given for sized hex constant.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:75: warning: extra digits given for sized hex constant.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:76: warning: extra digits given for sized hex constant.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:77: warning: extra digits given for sized hex constant.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:134: error: invalid module item.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:143: error: duplicate declaration for net or variable 'if_stall_nxt_pc' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:145: error: duplicate declaration for net or variable 'if_stall' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:146: error: duplicate declaration for net or variable 'if_flush' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:147: error: duplicate declaration for net or variable 'if_parcel' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:148: error: duplicate declaration for net or variable 'if_parcel_pc' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:149: error: duplicate declaration for net or variable 'if_parcel_valid' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:150: error: duplicate declaration for net or variable 'if_parcel_misaligned' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:153: error: duplicate declaration for net or variable 'mem_req' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:154: error: duplicate declaration for net or variable 'mem_ack' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:155: error: duplicate declaration for net or variable 'mem_adr' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:157: error: duplicate declaration for net or variable 'mem_q' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:159: error: duplicate declaration for net or variable 'mem_be' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:160: error: duplicate declaration for net or variable 'mem_misaligned' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:163: error: duplicate declaration for net or variable 'st_prv' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:166: error: duplicate declaration for net or variable 'dcflush_rdy' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:290: syntax error
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:41: error: invalid module item.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:44: error: duplicate definition for parameter 'XLEN' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:80: error: duplicate declaration for net or variable 'HCLK' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:80: error: duplicate declaration for net or variable 'HRESETn' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:83: error: duplicate declaration for net or variable 'ins_HSEL' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:84: error: duplicate declaration for net or variable 'ins_HADDR' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:85: error: duplicate declaration for net or variable 'ins_HRDATA' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:86: error: duplicate declaration for net or variable 'ins_HWDATA' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:87: error: duplicate declaration for net or variable 'ins_HWRITE' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:88: error: duplicate declaration for net or variable 'ins_HSIZE' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:89: error: duplicate declaration for net or variable 'ins_HBURST' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:90: error: duplicate declaration for net or variable 'ins_HPROT' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:91: error: duplicate declaration for net or variable 'ins_HTRANS' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:92: error: duplicate declaration for net or variable 'ins_HMASTLOCK' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:93: error: duplicate declaration for net or variable 'ins_HREADY' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:94: error: duplicate declaration for net or variable 'ins_HRESP' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:97: error: duplicate declaration for net or variable 'dat_HSEL' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:98: error: duplicate declaration for net or variable 'dat_HADDR' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:99: error: duplicate declaration for net or variable 'dat_HWDATA' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:100: error: duplicate declaration for net or variable 'dat_HRDATA' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:101: error: duplicate declaration for net or variable 'dat_HWRITE' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:102: error: duplicate declaration for net or variable 'dat_HSIZE' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:103: error: duplicate declaration for net or variable 'dat_HBURST' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:104: error: duplicate declaration for net or variable 'dat_HPROT' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:105: error: duplicate declaration for net or variable 'dat_HTRANS' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:106: error: duplicate declaration for net or variable 'dat_HMASTLOCK' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:107: error: duplicate declaration for net or variable 'dat_HREADY' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:108: error: duplicate declaration for net or variable 'dat_HRESP' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:114: error: duplicate declaration for net or variable 'dbg_ack' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:339: syntax error
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:365: error: invalid module item.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:374: error: duplicate declaration for net or variable 'dHWRITE' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:456: syntax error
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:475: error: invalid module item.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:476: error: duplicate definition for function 'hostcode_to_string' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:486: error: duplicate declaration for net or variable 'watchdog_cnt' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:514: syntax error
/home/antony/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv:66: error: invalid module item.
/home/antony/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv:92: error: duplicate declaration for net or variable 'mem_array' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv:104: error: duplicate declaration for net or variable 'dHTRANS' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv:105: error: duplicate declaration for net or variable 'dHWRITE' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv:119: syntax error
ivl: parse.y:2010: int VLparse(): Assertion `current_task == 0' failed.
Aborted
Makefile:60: recipe for target 'testbench_top.out' failed
make[1]: *** [testbench_top.out] Error 134
make[1]: Leaving directory '/home/antony/RV12/sim/ahb3lite/regression/bin/icarus'
Makefile:251: recipe for target 'icarus' failed
make: *** [icarus] Error 2
make: Leaving directory '/home/antony/RV12/sim/ahb3lite/regression/bin'
sphardy commented
All Roa Logic IP is written in System Verilog which is unfortunately not supported by Icarus.