drichmond
Building Secure, Usable, (Hardware) Systems since 1989.
University of California, Santa CruzSanta Cruz
Pinned Repositories
bsg_manycore
Tile based architecture designed for computing efficiency, scalability and generality
Challenge-II
PYNQ Hackathon 2017 Challenge 2
HOPS
Synthesizable Higher-Order Functions (Patterns) for C++
PYNQ-Hackathon-2017
General Repository for PYNQ Hackathon Resources
PYNQ-HLS
A Tutorial on Putting High-Level Synthesis cores in PYNQ
Python-Arduino-Command-API
A Python library for communicating with Arduino microcontroller boards
riffa-development
The RIFFA development repository
RISC-V-On-PYNQ
RISC-V Integration for PYNQ
riffa
The RIFFA development repository
PYNQ
Python Productivity for ZYNQ
drichmond's Repositories
drichmond/RISC-V-On-PYNQ
RISC-V Integration for PYNQ
drichmond/PYNQ-HLS
A Tutorial on Putting High-Level Synthesis cores in PYNQ
drichmond/HOPS
Synthesizable Higher-Order Functions (Patterns) for C++
drichmond/PYNQ-Hackathon-2017
General Repository for PYNQ Hackathon Resources
drichmond/Python-Arduino-Command-API
A Python library for communicating with Arduino microcontroller boards
drichmond/riffa-development
The RIFFA development repository
drichmond/Challenge-II
PYNQ Hackathon 2017 Challenge 2
drichmond/PYNQ
Python Productivity for ZYNQ
drichmond/pynq-copter
drichmond/PYNQ-Networking
Networking Overlay on PYNQ
drichmond/PYNQ-ZeroTier-Instructions
A short tutorial on how to install ZeroTier on PYNQ (2.3+)
drichmond/RV12
RISC-V CPU Core
drichmond/aws-fpga
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
drichmond/DRAMsim3
DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
drichmond/orca
RISC-V by VectorBlox
drichmond/readthedocs.org
source code to readthedocs.org
drichmond/riscv-tests
drichmond/rocket-chip
Rocket Chip Generator
drichmond/verilator
Verilator open-source SystemVerilog simulator and lint system
drichmond/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
drichmond/wireshark
Read-only mirror of Wireshark's Git repository. GitHub won't let us disable pull requests. ☞ THEY WILL BE IGNORED HERE ☜ Please upload them at https://code.wireshark.org/review/ .
drichmond/blog_yosyshq
drichmond/Piccolo
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
drichmond/pytest_utils
Package for producing Gradescope-compatible results.json files with Pytest tests
drichmond/sampa-public
the Sampa group website
drichmond/ShEF
Shielded Enclaves for Cloud FPGAs