KastnerRG/riffa

Issues

• Compilation/loading issues on Redhat 9 kernel 5.14.0-427.16.1.el9_4.x86_64

  #66 opened 2 months ago by bsobhani
  1

• riffa on ubuntu

  #58 opened 3 months ago by erginatalar
  11

• riffa.py ctype type error due to float type entered into fpga_send length argument

  #65 opened 5 months ago by dsdy120
  0

• UBUNTU18.0.4 failed to compile and install

  #51 opened 5 months ago by vicmaaa
  2

• fpga_send loop error

  #63 opened 8 months ago by xlyzzz
  0

• AC701 Sample Code C_NUM_CHNL = 3 Channel 3 Receive 0

  #62 opened 9 months ago by FrankChuKontex
  1

• ERROR: [VRFC 10-1775] range must be bounded by constant expressions

  #40 opened 6 years ago by YiSyuanChen
  3

• 8+ fpgas

  #59 opened 2 years ago by werwolf
  0

• chnl_tester state machine flow issue

  #30 opened 7 years ago by buttercutter
  8

• A question about testutil.c

  #57 opened 3 years ago by emesjx
  0

• Executed ./testutil 0 command displaying 0 devices, but use lspci displaying Xilinx Corporation Device 7028, anybody know why?

  #56 opened 3 years ago by qingcai52
  1

• UBUNTU20.0.4 failed to execute sudo make command

  #55 opened 3 years ago by qingcai52
  3

• Linux Driver Compilation Errors

  #26 opened 7 years ago by buttercutter
  9

• Build succes on Win10 but the resulting driver fails

  #54 opened 4 years ago by pmaBSA
  0

• Ubuntu 18.04 failed to compile

  #53 opened 4 years ago by robertstar
  4

• PCIe Gen2.0x16 or PCIe Gen3.0x16 support

  #49 opened 5 years ago by jixi2018
  1

• a big riffa bugs

  #50 opened 5 years ago by hushunkui
  0

• RIFFA Virtex 6 series BAR memory area read write

  #48 opened 5 years ago by briansune
  0

• Riffa simulation

  #47 opened 5 years ago by jixi2018
  0

• riffa python example showed different data between TX and RX buffers

  #44 opened 5 years ago by jixi2018
  3

• fpga_recv timeout

  #46 opened 5 years ago by bix010
  0

• Bandwidth drops for linux

  #29 opened 7 years ago by buttercutter
  13

• unable to resolve clog2s?

  #32 opened 6 years ago by Jzone315
  2

• file include issue on functions.vh

  #45 opened 5 years ago by gxflying
  0

• Cannot compile the driver on Ubuntu-18.04

  #43 opened 5 years ago by jixi2018
  5

• I want riffa 2.1 for spartan6

  #42 opened 5 years ago by tanbakoo
  0

• PCIe x1 gen 2

  #41 opened 6 years ago by CedricDly
  0

• bus master not enabled problem

  #8 opened 9 years ago
  13

• root scope declaration is not allowed in verilog 95/2K mode

  #27 opened 7 years ago by buttercutter
  5

• calculation of config_link_rate is off for VC709

  #39 opened 6 years ago by hmaarrfk
  0

• wSchedule throws warnings for not being set in Vivado 2018.3

  #38 opened 6 years ago by hmaarrfk
  6

• Why are the first four received words not as expected?

  #35 opened 6 years ago by Johnhave
  1

• Bulk data from PC to FPGA with slow user logic

  #34 opened 6 years ago by quangdaovu
  1

• riffa——learn

  #33 opened 6 years ago by moptutu
  0

• verilator testbench support

  #28 opened 7 years ago by buttercutter
  0

• Virtex5 ml505 boards support

  #25 opened 7 years ago by skoroneos
  0

• Computer simply does not boot up

  #24 opened 7 years ago by Adrizcorp
  0

• Cannot compile in linux

  #23 opened 7 years ago by NotZombieFood
  2

• Windows Handle Leak in fpga_recv()

  #22 opened 7 years ago by mpernambuco
  0

• riffa: BAR 0 incorrect length

  #21 opened 7 years ago by loiron
  3

• Orientation questions about the project

  #20 opened 7 years ago by Piedone
  4

• Xilinx tools not correctly implementing asynchronous FIFO.

  #13 opened 8 years ago by drichmond
  4

• Channel never acknowledge transaction

  #15 opened 8 years ago
  9

• CHNL_TX_DATA_REN up for extra cycle during 16 beat transfer

  #11 opened 8 years ago by mjacobsen
  2

• Problems with the pci_regs.h and slab.h on L4t 23.2 (Nvidia Jetson TX1)

  #7 opened 8 years ago by MrLent
  5

• RIFFA 2.2.1 driver not signed

  #10 opened 8 years ago by drichmond
  1

• RIFFA Driver fails on 32-bit ARM core with __aeabi_uldivmod during boot

  #9 opened 8 years ago by drichmond
  5

• RD_DATA width in tx_port_channel_gate_128

  #3 opened 9 years ago by dsidler
  2