/Implementing-a-Compact-SHA-256-in-FPGA-RTL

Compact and efficient implementation of the SHA-256 cryptographic hash algorithm in FPGA RTL. This repository includes Verilog-based RTL code optimized for FPGA resources, testbenches for functional verification, and synthesis reports. Ideal for secure and high-performance applications in cryptographic systems

Primary LanguageVerilogApache License 2.0Apache-2.0

Hi 👋, I'm sahil parmar

A passionate Electronic Engineer from India , VLSI Enthusiast

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Implementing-a-Compact-SHA-256-in-FPGA-RTL

Compact and efficient implementation of the SHA-256 cryptographic hash algorithm in FPGA RTL. This repository includes Verilog-based RTL code optimized for FPGA resources, testbenches for functional verification, and synthesis reports. Ideal for secure and high-performance applications in cryptographic systems

Compact SHA-256 Implementation in FPGA RTL

This repository contains a resource-efficient implementation of the SHA-256 cryptographic hash algorithm designed for FPGA devices. The project focuses on optimizing hardware resources while maintaining high performance and compliance with the SHA-256 standard (FIPS PUB 180-4).

Features

  • Compact Design: Optimized RTL implementation with minimal resource usage.
  • High Throughput: Designed for efficient parallel and pipelined operations.
  • Testbenches Included: Functional and timing verification.
  • FPGA Ready: Synthesis reports and implementation results for Xilinx/Intel FPGAs.

Project Structure

Design Details

  • SHA-256 Overview: Implements the 64-round iterative compression function as defined in FIPS PUB 180-4.
  • Core Components:
    • Message Scheduler: Expands the 512-bit input message into 64 words.
    • Compression Logic: Processes message blocks with the SHA-256 round functions.
    • State Registers: Maintains the working state of hash values.

Getting Started

  1. Clone the Repository:
    git clone https://github.com/yourusername/fpga-rtl-sha256.git
    cd fpga-rtl-sha256
    
    
    
    

Would you like help drafting a design_specification.md or creating testbenches for the project?