EASpiNN is the framework for asynchronous fashion Spiking Neural Networks acceleration on Xilinx SoC FPGA boards. The framework is scalable to run any dense layer networks on a given Xilinx SoC FPGA board. The networks have been evaluated on MNIST dataset.
git clone https://github.com/SFU-HiAccel/EASpiNN.git
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Evaluated hardware platforms:
- Xilinx SoC FPGA:
- Xilinx ZCU 104 Board
- Xilinx SoC FPGA:
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Software tools:
- HLS tool:
- Xilinx SDSoC 2019.1
- HLS tool:
Assuming you are in the project home directory of the checked out EASpiNN github repo.
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The following network configurations are evaluated.
Network Configuration Dense-1 Input-500-100-Output Dense-2 Input-1200-1200-Output -
Choose the network that you wish to run. Include the network in
tb.cpp
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Modify the configuartion in
includes/header.h
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The Unroll parameters for each board varies based on the available resources in the board.
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The parameters are choosen such that the resource utilization is around 80% utilized for all the resources (BRAM, URAM, DSP, LUT, FF).
- Create a project in SDSoC application for every network.
- Add all the files in the project.
- Software Mode
- Build the project.
- Hardware Mode
- Toggle
network
function to Hardware. - Set Hardware at 100MHz.
- Build the project.
- Toggle
- Software Mode
* Once the build is over, an SD Card folder is created.
* Copy the folder contents to an SD card.
* Insert the SD card to the FPGA board.
* Set the FPGA board in SD card boot mode.
* Boot the FPGA and visualize in serial monitor.
* Change the directory to mount (`cd /mnt`)
* Run the application `./snn <number of images>`.
If you have further questions about EASpiNN, please contact:
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Sathish Panchapakesan, MASc Student
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HiAccel Lab, Simon Fraser University (SFU)
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Email: sathishp@sfu.ca
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Website: http://www.sfu.ca/~sathishp/