SFU-HiAccel

Pinned Repositories

CHIP-KNN
[TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs
Language:C++13 3 18
EASpiNN
Language:C2 2 01
HiSpMV
[FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS
Language:C++6 1 00
Microbench_AlphaData
A microbenchmark program for architectural study of the Alpha Data board with Xilinx SDAccel
Language:C00
pasta
[FCCM 2023] PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs
Language:C9 7 01
rodinia-hls
FPGA version of Rodinia in HLS C/C++
Language:Roff30 5 08
SASA
[TRETS 2023] SASA: A Scalable and Automatic Stencil Acceleration Framework
Language:Python4 2 00
SQL2FPGA
[FCCM'23] SQL2FPGA: Automatic Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms
Language:Scala7 2 12
SyncNN
[FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.
Language:C++49 2 15
uBench
[FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
Language:C++28 4 03

SFU-HiAccel's Repositories

SFU-HiAccel/SyncNN
[FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.
Language:C++49 2 15
SFU-HiAccel/rodinia-hls
FPGA version of Rodinia in HLS C/C++
Language:Roff30 5 08
SFU-HiAccel/uBench
[FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
Language:C++28 4 03
SFU-HiAccel/CHIP-KNN
[TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs
Language:C++13 3 18
SFU-HiAccel/pasta
[FCCM 2023] PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs
Language:C9 7 01
SFU-HiAccel/SQL2FPGA
[FCCM'23] SQL2FPGA: Automatic Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms
Language:Scala7 2 12
SFU-HiAccel/HiSpMV
[FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS
Language:C++6 1 00
SFU-HiAccel/SASA
[TRETS 2023] SASA: A Scalable and Automatic Stencil Acceleration Framework
Language:Python4 2 00
SFU-HiAccel/EASpiNN
Language:C2 2 01
SFU-HiAccel/haoda
Hardware-Aware Optimization and Design Automation
Language:Python0 1 00
SFU-HiAccel/HT-Deflate-FPGA
Language:Verilog0 1 00
SFU-HiAccel/spark-sql-perf
Language:Scala0 1 00
SFU-HiAccel/vivado-hls-broadcast-optimization
[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
Language:Ada0 1 00
SFU-HiAccel/AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
Language:C++1 0
SFU-HiAccel/BitBlender
BitBlender is a scalable Bloom Filter accelerator, targeting FPGAs, written in TAPA High-Level Synthesis.
SFU-HiAccel/cs-259-19f
Language:C++1 0
SFU-HiAccel/dblp-playground
Asking questions about DBLP
SFU-HiAccel/Deflate-HLS
Language:C++0 0
SFU-HiAccel/heterocl
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
Language:C++1 0
SFU-HiAccel/HLS
Vitis HLS LLVM source code and examples
Language:C++1 0
SFU-HiAccel/HLS-Tiny-Tutorials
Language:C1 0
SFU-HiAccel/INSIDER-System
An FPGA-based full-stack in-storage computing system.
Language:Coq1 0
SFU-HiAccel/merlin-compiler
Language:C++1 0
SFU-HiAccel/minimap2-acceleration
Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: Open Source Repository
Language:C1 0
SFU-HiAccel/Sextans
An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
Language:C++1 01
SFU-HiAccel/ThunderGP
HLS-based Graph Processing Framework on FPGAs
Language:C++1 0
SFU-HiAccel/TopSort
Language:SystemVerilog0 0
SFU-HiAccel/tpch-spark
TPC-H queries in Apache Spark SQL using native DataFrames API
Language:C1 0
SFU-HiAccel/Vitis_Accel_Examples
Vitis_Accel_Examples
Language:C++1 0
SFU-HiAccel/Vitis_Libraries
Vitis Libraries