Repository containing the simulated schematics of logic gates, counters, adders and registers along with corresponding layouts for semiconductor design.
All files have been compiled and tested using DSCH2.exe (for schematics) and Microwind2.exe (for semiconductor layout design).
- AND, OR and NOT Gates (Inverter)
- Function Design with XOR and XNOR
- Half, Full and Ripple-Carry Adders
- D Flip-Flop and Latch
- JK Flip-Flop and Latch
- Dynamic and Domino Logic for AND and OR Gates