ShaheerSajid
Digital System Design, Embedded System Design, Computer Architecture, RTL to GDS flow using Cadence Design Systems
Pakistan
Pinned Repositories
AES-256-Matlab
AES 256 Implementation in Matlab
AES-256-Verilog
Synthesisable AES 256 Verilog Implementation
OpenCV-Maze-Solving
Solving a maze using OpenCV and path finding algorithms
PakFPU
Fully synthesizable and paramterizable, IEEE-754 compliant Floating Point Unit (FPU) in systemverilog. Supports fused multiply add, division and square root operations.
RISCV
32-bit soft RISCV processor for FPGA applications
RISCV-Compliant-Divider
Synthesisable RISCV 32bit Divider Verilog Implementation
RV32_with_MAC
SM4-Matlab
SM4 Encryption Implementation in Matlab
SM4-Verilog
Synthesizable SM4 Verilog Implementation
Water-Management-System
A device that monitors ad controls water consumption in public washrooms
ShaheerSajid's Repositories
ShaheerSajid/RISCV
32-bit soft RISCV processor for FPGA applications
ShaheerSajid/OpenCV-Maze-Solving
Solving a maze using OpenCV and path finding algorithms
ShaheerSajid/RISCV-Compliant-Divider
Synthesisable RISCV 32bit Divider Verilog Implementation
ShaheerSajid/AES-256-Matlab
AES 256 Implementation in Matlab
ShaheerSajid/AES-256-Verilog
Synthesisable AES 256 Verilog Implementation
ShaheerSajid/RV32_with_MAC
ShaheerSajid/SM4-Matlab
SM4 Encryption Implementation in Matlab
ShaheerSajid/SM4-Verilog
Synthesizable SM4 Verilog Implementation
ShaheerSajid/Water-Management-System
A device that monitors ad controls water consumption in public washrooms
ShaheerSajid/PakFPU
Fully synthesizable and paramterizable, IEEE-754 compliant Floating Point Unit (FPU) in systemverilog. Supports fused multiply add, division and square root operations.