ShaheerSajid/PakFPU
Fully synthesizable and paramterizable, IEEE-754 compliant Floating Point Unit (FPU) in systemverilog. Supports fused multiply add, division and square root operations.
SystemVerilog
Fully synthesizable and paramterizable, IEEE-754 compliant Floating Point Unit (FPU) in systemverilog. Supports fused multiply add, division and square root operations.
SystemVerilog