/Computer-Architecture-Lab-Experiments-F2023

ARM processor pipeline implementation. Featuring hazard unit, forwarding unit, SRAM & cache memory.

Primary LanguageVerilogMIT LicenseMIT

Computer Architecture Lab Projects

Implementing ARM processor in verilog for the computer architecture laboratory course at University of Tehran.

  • ARM Processor Implementation (ARM-1,..., ARM-4)
  • Forwarding Unit (ARM-5)
  • SRAM (ARM-6)
  • Cache Memory (ARM-7)