Pinned Repositories
Astra-Linux-labs
Operating systems on the example of linux
Auditory
17.02.2019
Casino
dsp-labs
Digital signal processing examples
ForPupils
Примеры кода с занятий
FPGA-practicum
learning about FPGA
FPGA_pract
Методические материалы курса "Практикум по ПЛИС"
riscv-simple-cpu
Creating a risc-v processor
spi-master-example
SPI-Master Controller example + peripheral devices simulation
SpringBootSample
Boot + JPA/DataSource prop + Security + Authorities
Shuregg's Repositories
Shuregg/riscv-simple-cpu
Creating a risc-v processor
Shuregg/SpringBootSample
Boot + JPA/DataSource prop + Security + Authorities
Shuregg/Astra-Linux-labs
Operating systems on the example of linux
Shuregg/Auditory
17.02.2019
Shuregg/Casino
Shuregg/dsp-labs
Digital signal processing examples
Shuregg/ForPupils
Примеры кода с занятий
Shuregg/FPGA-practicum
learning about FPGA
Shuregg/FPGA_pract
Методические материалы курса "Практикум по ПЛИС"
Shuregg/ialu-verification
Syntacore scr1 iALU verification example
Shuregg/miet-interfaces
Interfaces of computing systems
Shuregg/spi-master-example
SPI-Master Controller example + peripheral devices simulation
Shuregg/Frontend
Shuregg/Homework
C++ Sunday 15 PM
Shuregg/learning-C
Learning the C programming language
Shuregg/metrology
Shuregg/riscv-tests-intro
Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
Shuregg/SampleProject
Maven project to begin work
Shuregg/verif_elective_miet
verification practical lessons
Shuregg/xv6-os
learning about operating systems in xv6
Shuregg/xv6-riscv
Xv6 for RISC-V