SihaoLiu

Life is Analog

University of California, Los AngelesLos Angeles, California

Pinned Repositories

chipyard
Integrate OverGen with ChipYard SoC Generator
Language:C30
dsa-docs
Language:Python4 12 11
dsa-framework
Release of stream-specialization software/hardware stack.
Language:Python116 5 1223
dsa-riscv-ext
Language:C4 4 10
dsa-scheduler
Language:C++3 6 10
dsagen2
Domain-Specific Architecture Generator 2
Language:Scala200
chisel
Chisel: A Modern Hardware Design Language
Language:Scala00
chisel-testers2
Repository for chisel3 testers2 open alpha
Language:Scala00
diplomacy
Language:Scala0 0 00
felix-infra
The entry point of Felix Universe.
Language:Shell0 0 00

SihaoLiu's Repositories

SihaoLiu/chisel
Chisel: A Modern Hardware Design Language
Language:Scala00
SihaoLiu/chisel-testers2
Repository for chisel3 testers2 open alpha
Language:Scala00
SihaoLiu/diplomacy
Language:Scala0 0 00
SihaoLiu/felix-infra
The entry point of Felix Universe.
Language:Shell0 0 00
SihaoLiu/firesim
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud
Language:Scala00
SihaoLiu/fudian
Open source high performance IEEE-754 floating unit
SihaoLiu/libdfx
Sihao's Experimental Hack to test Device Tree Overlay with Overlay Generation (OverGen)
Language:C0 0
SihaoLiu/playground
chipyard in mill :P
SihaoLiu/rocket-chip
Rocket Chip Generator
SihaoLiu/SihaoLiu.github.io
Language:HTML
SihaoLiu/testchipip
Language:Scala0 0
SihaoLiu/Vitis_Libraries
Vitis Libraries
Language:C++0 0
SihaoLiu/XRT
Xilinx Run Time for FPGA
Language:C0 0