SihaoLiu

SihaoLiu's Stars

• PolyArch/dsa-framework

  Release of stream-specialization software/hardware stack.

  Language:Python11623

• PolyArch/dsagen2

  Domain-Specific Architecture Generator 2

  Language:Scala20

• PolyArch/dsa-riscv-ext

  Language:C4

• ucb-bar/chipyard

  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  Language:Scala1.6k630

• were/wdy-license

  The original repo of wdy licsense.

  91

• rapidstream-org/rapidstream-tapa

  RapidStream-TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.

  Language:C++15230

• Twine-Umich/Twine

  Language:Scala10

• chipsalliance/playground

  chipyard in mill :P

  Language:Scala7434

• riscv/riscv-v-spec

  Working draft of the proposed RISC-V V vector extension

  Language:Assembly955271

• sequencer/SoC

  Language:Scala42

• firesim/firesim

  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

  Language:Scala868229

• chipsalliance/firrtl

  Flexible Intermediate Representation for RTL

  Language:Scala720175

• chipsalliance/chisel

  Chisel: A Modern Hardware Design Language

  Language:Scala3.9k590

• SurviveSJTU/SurviveSJTUManual

  更新2008年版本的《上海交通大学生存手册》gitbook发布于https://survivesjtu.gitbook.io/survivesjtumanual/

  3.9k459

• llvm/circt

  Circuit IR Compilers and Tools

  Language:C++1.6k286

• YitaoLiang/Scala-LearnPsdd

  Learning the Structure of Probabilistic Sentential Decision Diagrams. https://web.cs.ucla.edu/~yliang/papers/uai2017.pdf

  Language:Scala75

• prakhar1989/awesome-courses

  :books: List of awesome university courses for learning Computer Science!

  56.7k8.1k

• arcade-lab/tia-infrastructure

  Language:SystemVerilog153

• nvdla/hw

  RTL, Cmodel, and testbench for NVDLA

  Language:Verilog1.7k567

• ucb-bar/riscv-sodor

  educational microarchitectures for risc-v isa

  Language:Scala677154