Tapeout: Tile_id straps cause DRC errors (M4CGRA)

[steveri]

To solve generator problems, the layout scripts carve out a little space in the CGRA tiles where M4 patch wires can be laid down to provide a constant ID for each tile. Unfortunately, the space is not large enough and, at the end, these wires touch the cell's M4 blockage and cause errors.

To get a clean error check, then, I delete all these path wires, or straps, before the DRC check, and then put them back afterwards.

Can we maybe think of a better way to implement the tile ID, and/or modify the script so as to prevent the DRC error?

In layout_Tile.tcl:

# Keep area around tile_id pins clear so we can route them at top level
createRouteBlk -name tile_id_rb -layer M4 -box [list 0 $tile_id_min_y $tile_id_max_x $tile_id_max_y]
createPlaceBlockage -name tile_id_pb -box 0 $tile_id_min_y $tile_id_max_x $tile_id_max_y

In floorplan.tcl

# Manually connect all of the tile_id pins
...
for {set row $min_row} {$row <= $max_row} {incr row} {
  for {set col $min_col} {$col <= $max_col} {incr col} {
    set tile_id_pins [get_pins $tiles($row,$col,name)/tile_id*]
    set num_id_pins [sizeof_collection $tile_id_pins]
    for {set index 0} {$index < $num_id_pins} {incr index} {
      ....
      create_shape -net $id_net_name -layer $connection_layer -rect $llx $lly $urx $ury
    }
  }
}