Issues
- 1
Fix/disable broken CI tests
#951 opened by steveri - 0
PD: well-tap / power-switch placement in mem tiles
#923 opened by steveri - 0
PD: Power domains break when PE features added
#922 opened by steveri - 12
PD: Cannot find RMUX cells during synthesis
#900 opened by steveri - 0
PD: glb_top silently failing LVS?
#845 opened by steveri - 5
PD: Scan regs appear out of thin air, prevent routing
#833 opened by steveri - 0
- 0
systemRDL support for CGRA units (tiles, interconnect)
#492 opened by kongty - 0
- 0
- 0
- 0
PD: Nondeterminism in PE tile
#803 opened by steveri - 3
PD: Tile builds silently fail during final GLS step
#791 opened by steveri - 0
PD/CI: Innovus/QRC "detected slow or hanging jobs"
#789 opened by steveri - 1
RTL step failed silently
#786 opened by steveri - 1
- 8
PD: Innovus fails in QRC
#761 opened by steveri - 3
PD: svdb directories too big
#769 opened by steveri - 1
Design: Global Buffer Test Checklist
#424 opened by kongty - 1
Cleanup filelist for global controller
#485 opened by kongty - 0
Tapeout: PHY bump final routing report
#543 opened by steveri - 0
stalling during config seems to break things
#534 opened by hofstee - 12
Cannot configure the PE reg mode when it's stalled
#536 opened by Kuree - 9
Long RTL generation times
#448 opened by alexcarsello - 1
Tapeout: Better bumps
#493 opened by steveri - 0
Add register for stall signal at each io core
#484 opened by kongty - 0
- 0
Tapeout: useless corner cell, rte net manipulations?
#444 opened by steveri - 11
coreir core dump during mem tile generation
#428 opened by steveri - 1
mflowgen: gdsmerge/outputs needs input from stdin?
#418 opened by steveri - 10
coreir/pycoreir requirements
#417 opened by steveri - 3
mflowgen: Makefile error is ignored
#415 opened by steveri - 3
magma/peak dependency problems in requirements.txt
#414 opened by steveri - 1
- 0
Tapeout: Overlapping DTCD cells
#408 opened by steveri - 0
Tapeout: DTCD cell blockages cause DRC errors
#407 opened by steveri - 0
Tapeout: iphy pins tied to ground, why?
#405 opened by steveri - 0
Tapeout: Overlapping IO pads
#399 opened by steveri - 0
Tapeout: Final error check for Innovus
#397 opened by steveri - 0
Tapeout: M8 blockage across entire top of chip.
#396 opened by steveri - 1
Tapeout: 45-degree RDL routes? Or manhattan?
#389 opened by steveri - 1
- 0
Tapeout: Bottom-row ICOVL cells block power straps
#395 opened by steveri - 2
- 0
Tapeout: Tile_id straps cause DRC errors (M4CGRA)
#394 opened by steveri - 1
Tapeout: Weird big blockages on two ICOVL cells cause thousands of DRC violations
#392 opened by steveri - 0
Tapeout: ICOVL halos and blockages (SPACE1703)
#393 opened by steveri - 1
Tapeout: DRC violations in stage 5 (routing)
#386 opened by steveri - 0
Tapeout: Constraint not on manufacturing grid
#383 opened by steveri - 2
Tapeout: RDL blockages?
#382 opened by steveri