Tapeout: M8 blockage across entire top of chip.

[steveri]

After all the tcl scripts have run and we're ready to stream out the gds tape, there appears to still be a massive M8 blockage across the top of the chip. It goes all the way from left to right edge, beginning at the top of the chip and coming down until it's level with the bottom of the iphy block.

Looks like it comes from the phy_placement.tcl script (which is called from within floorplan.tcl)

# M8 blockage covering pad frame bracketing (butter)phy block left, right, top
create_route_blockage -area    0 $origin_phy_y  100 [expr $origin_phy_y+$phy_height] -layer M8
create_route_blockage -area 4800 $origin_phy_y 4900 [expr $origin_phy_y+$phy_height] -layer M8
create_route_blockage -area    0               4800 4900 4900 -layer M8

The blockage doesn't look useful b/c the region is already striped throughout with VDD/VSS wires.

Anyway, I currently delete the blockage for final error check before final stream-out (it causes like 300 DRC errors, one for each M8 power stripe).

Questions:

• why is the M8 blockage there?
• is it useful?
• should it be deleted at some point? when?