Tapeout: iphy pins tied to ground, why?

[steveri]

During floorplanning, the iphy/butterphy pins all get tied to ground, mostly. Later, this causes DRC errors (see below). Innovus seems to be complaining that the tielo net is shorted to ground (but wasn't that the point!!?)

Regular Wire of Net FE_OFN1632371_LTIELO_164_NET & Special Wire of Net VSS
Type:	Metal Short 
bbox = (2393.676, 4358.604) (2395.09, 4358.964)

Anyway, rather than spend time tracking down what's really supposed to happen and how to better prevent the DRC errors, I simply disconnect the tielo pins

########################################################################
# ??? sr 1912 iphy pins are tied low by the above command
#   "connect_global_net VSS -type tielo"
# b/c they have this property .constant==0 for some reason
# Keeping them tied low is causing problems later so I'm disconnecting them:
set iphy_tielo_pins [ \
  get_db pins -if { .constant != no_constant && .name == *iphy* }
]
puts "@file_info # "
puts "@file_info # Disconnect iphy pins from tielo"
puts "@file_info: BEFORE (should say net=VSS)"
foreach p $iphy_tielo_pins {
    # pin_name "iphy/foo" => "foo"
    set pin_name [ get_db $p .name ]
    set pin_name [ string range $pin_name 5 end ]
    puts "@file_info:     net=[ get_db $p .net ] $p"
    disconnect_pin -inst iphy -pin $pin_name -net VSS
}

Also see git diff ff230912 97d5da8

If anyone has insight/comment about this, please speak up. Meanwhile I leave this issue as a record of what happened and why.

How to detect tielo pins:

get_db pins -if {
  .constant == 0
  && .name == *phy*
  }

pin:GarnetSOC_pad_frame/IOPAD_jtag_intf_i_phy_tck/ST
pin:GarnetSOC_pad_frame/IOPAD_jtag_intf_i_phy_tck/PE
...

(Includes 40 JTAG pins, plus all the clock pins etc.)

Tielo pins get tied low in floorplan.tcl:
connect_global_net VSS -type tielo