StanfordAHA/garnet

Issues

• Tapeout: ICOVL halos and blockages (SPACE1703)

  #393 opened 5 years ago
  0

• Tapeout: Weird big blockages on two ICOVL cells cause thousands of DRC violations

  #392 opened 5 years ago
  1

• Tapeout: 45-degree RDL routes? Or manhattan?

  #389 opened 5 years ago
  1

• Tapeout: False(?) DRC violations on 45-degree wires - 90-degree turns

  #388 opened 5 years ago
  1

• Tapeout: False(?) DRC violations on 45-degree wires - runlength spacing

  #387 opened 5 years ago
  2

• Tapeout: DRC violations in stage 5 (routing)

  #386 opened 5 years ago
  1

• Tapeout: Constraint not on manufacturing grid

  #383 opened 5 years ago
  0

• Tapeout: RDL blockages?

  #382 opened 5 years ago
  2

• What's up with cutmodule?

  #377 opened 5 years ago
  3

• Tapeout: Where do IOPAD offsets come from?

  #376 opened 5 years ago
  3

• Tapeout: Does IOPAD ordering matter?

  #375 opened 5 years ago
  2

• Tapeout: Top-level LVS fails for lack of memory

  #371 opened 5 years ago
  1

• Genus 19

  #369 opened 5 years ago
  0

• Tapeout: LVS errors in final gds

  #367 opened 5 years ago
  7

• Tapeout: DRC errors in Tile_MemCore

  #366 opened 5 years ago
  0

• Tapeout: DRC errors in Tile_PE

  #365 opened 5 years ago
  0

• Partition global buffer for physical design

  #363 opened 5 years ago
  1

• Use master hwtypes

  #360 opened 3 years ago
  3

• Tapeout: FE_FILLER cells and shorted nets

  #356 opened 5 years ago
  9

• Tapeout: eval_legacy / obsolete commands in tcl scripts

  #355 opened 5 years ago
  0

• Tapeout: Route script takes forever

  #353 opened 5 years ago
  6

• OSError: libverilogAST.so: cannot open shared object file: No such file or directory

  #352 opened 5 years ago
  3

• Tapeout: Fill script takes forever

  #351 opened 5 years ago
  3

• Can we add a `timescale directive to the generated garnet.v?

  #350 opened 5 years ago
  0

• Segmentation fault during layout / floorplanning

  #349 opened 5 years ago
  4

• Inconsistent sram-cell lists in tapeout scripts

  #346 opened 5 years ago
  1

• run_layout errors: "cannot find [sram] library cells"

  #345 opened 5 years ago
  9

• too many optimization passes during layout?

  #343 opened 5 years ago
  2

• "official" layout_Tile script does not work with innovus 19

  #342 opened 5 years ago
  2

• Why does mapping use so much memory?

  #341 opened 5 years ago
  5

• One-Button PD Flow On Each Check-in: Tasklist

  #340 opened 5 years ago
  3

• PWR_AWARE value in scripts?

  #339 opened 5 years ago
  1

• innovus v. genus

  #338 opened 5 years ago
  2

• garnet has fifty branches (ish)

  #337 opened 5 years ago
  3

• MASTER BRANCH FAILING IN TRAVIS (libverilogAST missing)

  #336 opened 5 years ago
  5

• Run pd flow for PE tile on each check-in

  #335 opened 5 years ago
  7

• Tiled layer with global buffer

  #331 opened 5 years ago
  1

• Physical design flow constructed using gemstone

  #329 opened 5 years ago
  0

• Interconnect test fails when input stream fanout to all tracks.

  #308 opened 6 years ago
  1

• Fanout io signals

  #304 opened 6 years ago
  1

• Change stall signal bit width to 1 from 4

  #303 opened 6 years ago
  1

• Inferred latch in global controller

  #297 opened 6 years ago
  2

• Add IO placement function

  #296 opened 6 years ago
  2

• Default const instead of routes in the control signals for MEM core

  #292 opened 6 years ago
  1

• Unused 1bit data coming out from cgra io_tile should set to 0 after configuration.

  #286 opened 6 years ago
  3

• Fix SRAM read config data

  #285 opened 6 years ago
  0

• Create gate-level tests from PD

  #279 opened 6 years ago
  0

• Refactor memory tests

  #267 opened 6 years ago
  0

• Genus segfaults during power aware synthesis of memory tile

  #263 opened 6 years ago
  6

• Memory tile area and timing

  #262 opened 6 years ago
  2