Can we add a `timescale directive to the generated garnet.v?

[hofstee]

I don't think there is any timescale information for the design anywhere in the generated verilog. This trips up VCS in particular which seems to assume a timescale of 1s if none is specified. Since we are designing with a frequency target in mind, it might not be a bad idea to have the timescale information in the files. That way if anyone is using #delays in their code to model physical units we can make sure things will still simulate accurately.

One issue this might cause is that IIRC NCSim will error if some modules don't contain timescale information. I'm not sure how other simulators handle this.