StanfordAHA/garnet

Tapeout: Bottom-row ICOVL cells block power straps

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Note: this issue is mostly a combination FYI and to-do list, since I already implemented the fix.

The Problem: It looks like the chip was crafted such that VDD bumps near each corner are supposed to connect to nearby VDD IO pads. The IO pads in turn connect to nearby IO stripes with multiple m4 wire straps. Unfortunately the ICOVL cell array blocks these straps and causes DRC errors. In the image below, the white square is 26 DRC errors where the m4 straps run over the ICOVL cell

bottomrow1

I understand that the previous solution was to delete the offending straps. I opted for a different fix. What I do is 1) use a custom io_file to scoot the IO pad over to the left a bit and 2) move the ICOVL array to the right, so that 3) IOPAD no longer sits under ICOVL array. This is a 2-line change, one in the hacked io_file and one in gen_floorplan.tcl:

% git diff b732c3 4f9448
--- a/tapeout_16/examples/io_file_hacked
# move IO pad 100u to the left
-               (inst name="IOPAD_bottom_VDD_0" offset=450)
+               (inst name="IOPAD_bottom_VDD_0" offset=350)

--- a/tapeout_16/scripts/vlsi/flow/scripts/gen_floorplan.tcl
# move ICOVL array 340 microns to the right
+  # gen_fiducial_set 100.0 58.70 ll false
+  gen_fiducial_set 440.0 58.70 ll false

Before:
bottomrow_before

After:
bottomrow_after2

Still to do:

  • update the script that generates io_file so don't have to use custom handbuilt version
  • check with Calibre to see if ICOVL cells are okay in their new position.