StanfordAHA/garnet

PD: GLB-tile routing track too small for 8-bank (256K) version

Closed this issue · 0 comments

PROBLEM:
Increasing glb tile SRAM size from 64K to 256K results in placement errors. Apparently, there is not enough space for routing/buffering wires.

SOLUTION: It looks like floorplan.tcl has a way to add horizontal space to the tile as the number of SRAM banks increase, using "magic numbers" e.g.

  % cat glb_tile/custom-init/outputs/floorplan.tcl
    # Magic number
    set sram_spacing_x_even 0
    set sram_spacing_x_odd 15

I found that sram_spacing_x_odd does nothing (?), at least not for either of mem_size=64K (one bank of four SRAMs) or mem_size=256K (two banks of eight SRAMs each). So I changed sram_spacing_x_even to 15, which added 15u of extra horizontal space to the 256K version only, and that was apparently enough to allow the build to complete successfully:

I will be filing a git pull to fix this issue in the very near future.