StanfordAHA/lake
Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.
PythonBSD-3-Clause
Issues
- 0
Improving Opal 4/22/24
#193 opened by Joejoedesu - 0
Stencil Valid Config Parsing Error
#124 opened by joyliu37 - 0
- 0
Control signal polarity in tech maps
#120 opened by alexcarsello - 1
- 0
- 4
Chaining logic needs disable
#36 opened by mbstrange2 - 0
- 6
Wrapper for verilog generation does not work?
#71 opened by dillonhuff - 1
Create a chain of and gate use reduce in Kratos
#41 opened by joyliu37 - 2
- 0
clk_en bypass for SRAM
#34 opened by mbstrange2 - 0
Default __main__ missing/old
#25 opened by Kuree - 1
- 1
Error out with ncsim
#17 opened by Kuree