SupZQ's Stars
ltzheng/CurriculumMARL
Code of "Towards Skilled Population Curriculum for MARL" + Implementation of Curriculum MARL algorithms based on Ray
ScarboroughCoral/CSAPP-Lab
:smile: "Computer Science, a programmer's perspective 3th edition" lab code
Exely/CSAPP-Labs
Solutions and Notes for Labs of Computer Systems: A Programmer's Perspective 3rd Editon // 《深入理解计算机系统》第三版的实验文件、解答与笔记
DreamAndDead/CSAPP-3e-Solutions
CSAPP 3e Solutions, migrated to github.io from gitbook.io which is being shut down.
xr1s/CSAPP
Homework solutions for CSAPP (a.k.a. Computer System A Programmer's Perspective) Third Edition.
aliireza/ddio-bench
Reexamining Direct Cache Access to Optimize I/O Intensive Applications for Multi-hundred-gigabit Networks
Xtra-Computing/ThunderRW
Source code of "ThunderRW: An In-Memory Graph Random Walk Engine" published in VLDB'2021 - By Shixuan Sun, Yuhang Chen, Shengliang Lu, Bingsheng He and Yuchen Li
plasma-umass/NextDoor
Graph Sampling using GPU
flashmobwalk/flashmob
FlashMob is a shared-memory random walk system.
Tyrant1337/Lu-Decomposition-in-Parallel
This project uses openMP, MPI, and Cuda to solve lu decomposition
futurewei-cloud/chogori-platform
zyearn/TCNVMalloc
TCNVMalloc is an efficient wear-aware allocator for Non-Volatile Memory
deecamp2019-group20/botzone
botzone FightTheLandlord 脚本
fajieyuan/SIGIR2020_peterrec
Universal User Representation Pre-training for Cross-domain Recommendation and User Profiling
oscomp/proj28-3RMM
一个可靠、健壮、实时的内存分配器,支持内存冗余,抗单粒子翻转。
gdut-yy/PL0
GDUT 编译原理课程的课内实验和课程设计(含报告)
wolverinn/Waking-Up
计算机基础(计算机网络/操作系统/数据库/Git...)面试问题全面总结,包含详细的follow-up question以及答案;全部采用【问题+追问+答案】的形式,即拿即用,直击互联网大厂面试;可用于模拟面试、面试前复习、短期内快速备战面试...
TheLitFire/USTC-CS-CheatPapers
Cheat papers for CS courses in USTC. USTC计算机半开卷大抄
fajieyuan/WSDM2019-nextitnet
Generative model for sequential recommendation based on Convolution Neural Networks (CNN))
15172658790/Blog
**科学技术大学计算机学院课程资源(https://mbinary.xyz/ustc-cs/)
USTC-Resource/USTC-Course
:heart:**科学技术大学课程资源
zhongyuchen/mips-32bit
Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board