Tito047

I was created to create....

India

Pinned Repositories

2-STAGE-OTA-CALCULATOR
Language:Python00
47
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avsdmux2x1_3v3
Language:Shell00
Circuits
Contains Circuits helpful in understanding concepts.
Language:AGS Script00
eagle-lib
Set of custom elements for Eagle CAD
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Eagle-libraries
My collection of Eagle libraries
Language:HTML00
eagle-library
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ECG-signal-analysis
Language:Python00
Face-velocity-measurement
Measures the velocity of the face...
Language:C++00
Low-cost-ECG-device
Language:Python00

Tito047's Repositories

Tito047/2-STAGE-OTA-CALCULATOR
Language:Python00
Tito047/47
00
Tito047/avsdmux2x1_3v3
Language:Shell00
Tito047/Circuits
Contains Circuits helpful in understanding concepts.
Language:AGS Script00
Tito047/eagle-lib
Set of custom elements for Eagle CAD
00
Tito047/Eagle-libraries
My collection of Eagle libraries
Language:HTML00
Tito047/eagle-library
00
Tito047/ECG-signal-analysis
Language:Python00
Tito047/Face-velocity-measurement
Measures the velocity of the face...
Language:C++00
Tito047/Low-cost-ECG-device
Language:Python00
Tito047/machine-learning-coursera-1
This repo is specially created for all the work done my me as a part of Coursera's Machine Learning Course.
Language:MATLAB
Tito047/mcuoneclipse
McuOnEclipse Processor Expert components and example projects
Language:Batchfile
Tito047/microwatt
A tiny Open POWER ISA softcore written in VHDL 2008
Tito047/Mini-ECG
Language:Python
Tito047/MOS-Amplifiers
This repository contains a collection of codes which will help in understanding of Mosfet amplifiers.
Tito047/nandland
All code found on nandland is here. underconstruction.gif
Tito047/NIR_PLL
Language:Verilog
Tito047/Numerical-methods
Contains a list of codes which is used in solving polynomials..
Language:C
Tito047/RAM
Language:Shell
Tito047/riscv-isa-manual
RISC-V Instruction Set Manual
Tito047/Signal-Analysis
Tito047/skywater-pdk-libs-sky130_fd_pr
Tito047/SparkFun-Eagle-Libraries
SparkFun's Public Eagle PCB Footprints using Eagle 6.0+
Tito047/Swarm
Tito047/VHDL-Basics
This repository consists of basic VHDL codes intended for a brief revision.
Language:VHDL
Tito047/vlsi_design-assignments
Tito047/vsdmixedsignalflow
This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.
Tito047/vsdsram
Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
Tito047/yo