UCLA-VAST/AutoBridge
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
C++MIT
Issues
- 1
- 1
Balance SLR crossing on the two sides
#5 opened by Licheng-Guo - 1
4-way partition
#17 opened by Licheng-Guo - 1
Add constraints for SLR crossing
#16 opened by Licheng-Guo - 1
`src/pyproject.toml` breaks editable installation
#19 opened by Blaok - 5
Issue with Vitis HLS 2021.2
#14 opened by Oxygen-Chu - 3
Question about Hard-coded Resource Information
#13 opened by RipperJ - 5
Code Organization
#9 opened by Licheng-Guo - 1
- 0
Integrate with AutoParallel
#3 opened by Licheng-Guo - 9
[Error Report] Benchmarks do not run
#8 opened by luojw-dwr - 2
[Error Report] Regression does not run
#7 opened by luojw-dwr - 1
- 1
Add error message when ILP failed
#2 opened by Licheng-Guo - 3
Attach images to README.md
#1 opened by Licheng-Guo