UCSBarchlab/PyRTL

Issues

• Add a helper function to encode 1-hot to binary

  #455 opened 3 months ago by vaaniarora
  2

• Add wire_struct and wire_matrix examples

  #448 opened 7 months ago by fdxmw
  0

• Improve block visualization

  #451 opened 7 months ago by fdxmw
  0

• Improve handling of signed numbers

  #450 opened 7 months ago by fdxmw
  0

• Improve notebook support

  #449 opened 7 months ago by fdxmw
  0

• Python 3.10 Support

  #421 opened 7 months ago by benjaminmordaunt
  2

• Optimize is currently missing the elimination of "double not"

  #447 opened 7 months ago by timsherwood
  0

• Explicit reset signal?

  #445 opened 8 months ago by cbatten
  2

• Right shift operation semantics difference

  #443 opened 8 months ago by timsherwood
  0

• ROM not working as expected (16 bit address & 16 bit data)

  #423 opened 2 years ago by kfeiste
  1

• Wires used but never driven

  #422 opened 2 years ago by JulianKemmerer
  6

• "toplevel" in verilog output is hardcoded

  #420 opened 3 years ago by bjourne
  0

• Import `collections.abc.Mapping`

  #410 opened 3 years ago by corwin-of-amber
  2

• Add bitmasked write to memories

  #418 opened 3 years ago by timsherwood
  1

• fixed point

  #417 opened 3 years ago by timsherwood
  1

• Missing SDFF_PP1 circuit model yosys primitive

  #411 opened 3 years ago by JulianKemmerer
  5

• Add unit tests for different types of possible flip-flops importable as BLIF

  #414 opened 3 years ago by mdko
  1

• Update Sphinx theme

  #264 opened 3 years ago by timsherwood
  0

• Wavedrom output issues

  #273 opened 3 years ago by ti6wb
  1

• Find better way to handle special WireVector subclasses like `_MemIndexed`

  #406 opened 3 years ago by mdko
  0

• Register update on Negative edge

  #370 opened 4 years ago by tahaghauri
  1

• AES example not executable

  #379 opened 4 years ago by jemcmahan13
  0

• Add automatic testing of Jupyter notebook files

  #376 opened 4 years ago by mdko
  1

• Documentation missing interface for Block

  #375 opened 4 years ago by timsherwood
  0

• Improve visualization of nets where order of incoming edges matters

  #363 opened 4 years ago by mdko
  0

• Graph output doesn't display multiple identical edges properly

  #357 opened 4 years ago by mdko
  0

• Implement wrap_around in the barrel_shifter

  #355 opened 4 years ago by mdko
  0

• Update `clone_wire` to be more precise about limitations, or make safer

  #348 opened 4 years ago by mdko
  0

• Documentation for memblocks has no max write ports

  #268 opened 4 years ago by dkupsh
  0

• Comment Typo

  #266 opened 4 years ago by v-benenati
  1

• Extract area delay from yosys

  #274 opened 4 years ago by ti6wb
  1

• Allow Use of Negative IntEnums

  #317 opened 4 years ago by mdko
  2

• Add verification supports to PyRTL

  #275 opened 4 years ago by tunlee
  1

• Don't Cares in Pattern Matching

  #324 opened 4 years ago by BracketMaster
  5

• FastSimulation and CompiledSimulation not showing up in documentation

  #325 opened 4 years ago by timsherwood
  0

• Improve CompiledSimulation Iteration over Memory

  #320 opened 4 years ago by mdko
  0

• Option for non-deterministic order of temporary variables in verilog

  #293 opened 4 years ago by aomglova
  0

• Example project with Xilinx Zynq 7010 or similar SoC hardware

  #272 opened 5 years ago by lneuhaus
  5

• Implementing signed multiplication for Verilog export

  #276 opened 5 years ago by lneuhaus
  2

• Make FastSimulation faster by combining it with Simulation

  #265 opened 5 years ago by drholmie
  0

• BRAMs as separate modules

  #262 opened 5 years ago by gtzimpragos
  1

• Using output as a source (rather than a dest) throw internal error instead of user error

  #263 opened 6 years ago by timsherwood
  0

• Declaring WireVectors named "tmp"

  #257 opened 6 years ago by kyliehuch
  1

• `from pyrtl.rtllib import adders`

  #261 opened 6 years ago by adaezy
  2

• estimate.TimingAnalysis().max_length() has no units in documentation

  #259 opened 6 years ago by dkupsh
  2

• Use of Memory results in TypeError

  #260 opened 6 years ago by dkupsh
  2

• Error loading pickled working block

  #258 opened 6 years ago by JacquelineMai
  2

• Using matrix of wirevectors resulted in op_param out of bounds error

  #256 opened 6 years ago by JacquelineMai
  2

• Towards multiple clock domains — asynchronous inputs

  #253 opened 6 years ago by abe-k
  1

• Help with design low-level HDL language

  #251 opened 6 years ago by XVilka
  1