VLSI Design & Automation Group

UC Santa Cruz VLSI Design and Automation research lab

Santa Cruz, CA

Pinned Repositories

chip-tutorials
Language:Python5 2 04
lithosim
This is a very basic lithography simulation and pixel-based OPC tool.
Language:C45 1 09
OpenCache
An open-source custom cache generator.
Language:Python34 1 55
OpenRAM
An open-source static random access memory (SRAM) compiler.
Language:Python958 57 202238
openram_testchip
https://caravel-user-project.readthedocs.io
Language:Verilog9 0 03
OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
Language:Verilog4 1 00
OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Language:Verilog00
puffery
Tools for PUF analysis
Language:Python11 5 04
sky130_sram_macros
Language:SourcePawn14 3 215
vlsida-eda
Conda recipes for VLSIDA projects.
Language:Shell5 1 00

VLSI Design & Automation Group's Repositories

VLSIDA/OpenRAM
An open-source static random access memory (SRAM) compiler.
Language:Python958 57 202238
VLSIDA/lithosim
This is a very basic lithography simulation and pixel-based OPC tool.
Language:C45 1 09
VLSIDA/OpenCache
An open-source custom cache generator.
Language:Python34 1 55
VLSIDA/sky130_sram_macros
Language:SourcePawn14 3 215
VLSIDA/puffery
Tools for PUF analysis
Language:Python11 5 04
VLSIDA/openram_testchip
https://caravel-user-project.readthedocs.io
Language:Verilog9 0 03
VLSIDA/chip-tutorials
Language:Python5 2 04
VLSIDA/UCSC_ML_suite
Language:Verilog55
VLSIDA/vlsida-eda
Conda recipes for VLSIDA projects.
Language:Shell5 1 00
VLSIDA/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
Language:Verilog4 1 00
VLSIDA/openram_testchip2
Language:Verilog3 3 5
VLSIDA/SKY130_for_KLayout
KLayout technology files for Skywater SKY130
Language:Ruby2 0 00
VLSIDA/storage
Language:Verilog2 2 01
VLSIDA/gf180_fd_bd_sram
1 1 0
VLSIDA/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Language:SourcePawn1 0 00
VLSIDA/sky130_klayout_pdk
Skywater 130nm Klayout Device Generators PDK
Language:Python1 0 0
VLSIDA/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Language:Verilog00
VLSIDA/bsg_fakeram
fakeram generator for use by researchers who do not have access to commercial ram generators
Language:Python0 0
VLSIDA/calbridge_git_tutorial
Demo page for the CalBridge git tutorial
4 03
VLSIDA/FakeRAM2.0
Language:Python0 0
VLSIDA/klayout
klayout tech files
Language:Ruby1 01
VLSIDA/openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
Language:Python0 0
VLSIDA/sky130-validation
Silicon validation projects for SKY130 stuff
Language:C++0 0
VLSIDA/sky130_fd_bd_sram
1 0
VLSIDA/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Language:Python0 0
VLSIDA/skywater-pdk-libs-sky130_fd_bd_sram
0 0
VLSIDA/skywater-pdk-libs-sky130_fd_pr_reram
SKY130 ReRAM and examples (SkyWater Provided)
0 0
VLSIDA/tt25a_openram_testchip
Language:Verilog0 0
VLSIDA/vlsida-codespace
Language:Shell
VLSIDA/vlsida-openroad
Language:Dockerfile1 0