Issues
- 7
Error in SRAM creation with banks
#228 opened by KanishR1 - 1
Fails to compile with sky130-pdk
#255 opened by ahmedshakill - 0
- 0
- 0
Error Occurred in Delay Generation
#252 opened by YWJ226 - 1
Assertion Error in SRAM Generation with Specific word_size and num_words Configurations
#251 opened by riagus99 - 1
Question: Available routing layers
#250 opened by FriedrichWu - 2
Modiftying Openram
#249 opened by Redroom20 - 3
- 3
Error in using sram macro(tiny) in openlane2
#247 opened by FriedrichWu - 3
- 8
Runtime
#245 opened by mbautista-lab - 1
Not generate certain module
#244 opened by YWJ226 - 0
- 14
Power estimation seems too high
#242 opened by LucaMartis00 - 10
Question: What is the correct allignment in SKY130? Intermediate Pins are not connected to the grid. Likely user mistake.
#239 opened by c-93 - 1
Support for ASAP7 PDK
#241 opened by mbautista-lab - 0
- 3
Import custom file
#238 opened by YWJ226 - 7
Importing a custom GDS file.
#235 opened by YWJ226 - 2
No liberty file is created for ROMs
#237 opened by galv - 1
Routing error due to high (vertical) density?
#236 opened by c-93 - 0
- 1
multiports bitcell
#233 opened by YWJ226 - 3
ROM >= 8k fails to build
#232 opened by urish - 0
ROM dump + replace contents
#231 opened by urish - 4
Support for PROBE PDK
#229 opened by glzhou97 - 1
LVS mismatch errors in SKY130 SRAM
#217 opened by KEVIN09876 - 5
How to generate an SRAM with more than two ports?
#221 opened by HotCoCoC - 1
openram.py doesn't exist in any tree
#227 opened by msarwarx1 - 3
Unable to read configuration file
#226 opened by cannotgetaname - 1
Feature request: PROM
#224 opened by spth - 5
Use Volare as PDK version manager
#218 opened by mole99 - 1
Support for ASAP7 (open source 7nm PDK)
#222 opened by StephenMoreOSU - 0
LVS mismatch for some sky130 example SRAMs
#220 opened by ubfx - 2
ROM signal names do not match model
#216 opened by mole99 - 4
4 test case failed for freepdk and scn4m
#209 opened by z4fang - 2
Virtuoso Layout using freepdk45
#214 opened by tomaschoi03 - 4
Generating bit cell array with custom bit cell.
#213 opened by tomaschoi03 - 11
Pin iterator not found error in hierarchy_layout.py
#211 opened by htm23x - 4
scn3me_subm tech CellProperties error
#212 opened by htm23x - 4
sram_compiler.py - python 3.8.18 posixpath error
#207 opened by htm23x - 0
Errors on characterization process
#206 opened by andreili - 1
Support for IHP PDK
#208 opened by htm23x - 5
- 1
Guideline needed for the insertion of a foreign pdk like gpdk45 into OpenRAM flow
#205 opened by faisaladilquadery - 5
- 3
- 13
installaion problem and configuratiom problem
#202 opened by haotommy - 8
Anaconda install problem
#201 opened by haotommy