netgen
There are 16 repositories under netgen topic.
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
VLSIDA/OpenRAM
An open-source static random access memory (SRAM) compiler.
iic-jku/osic-multitool
JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
SiavashMT/OCT-MPS
Massively Parallel Simulator of Optical Coherence Tomography (OCT-MPS)
sgherbst/sky130-hello-world
Minimal SKY130 example with self-checking LVS, DRC, and PEX
vsdip/vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).
netgen/NetgenEnhancedBinaryFileBundle
Netgen Enhanced Binary FIle Bundle is an eZ Platform bundle that provides a field type that reimplements ezbinaryfile field type.
adam-rumpf/pynetgen
A Python module for generating random network flows problem instances in DIMACS graph format.
efabless/sak-deprecated
SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA
3x10e8/fossi_cochlea
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel
dfritschy/ezplatform-gatsby
A simple study showing eZ Platform content consumed by Gatsby via GraphQL
vadim-z/lua-femtk
Lua modules to work with FEA data
watbulb/tt-toolchain-build
A Linux-Local Installation of TT tools at version parity with TinyTapeout Selected Versions (see branch name)
netgen/ibexa-scheduled-visibility
Content visibility scheduling for Ibexa CMS
the-pinbo/EC302-VLSI-Design-Lab
EC302-VLSI-Design-Lab
tpaviot/netgen-conda
Conda build for netgen mesher