bharath19-gs

6T_SRAM_CELL

SRAM means Static Random Access Memory. The SRAM cell that we considered in this paper was 6T SRAM cell which consists of two crossly coupled inverters and access transistors to read and write the data. In case of the SRAM cell the memory built is being stored around the two cross coupled inverters.

AdvancedPhysicalDesign-with-OpenLane-using-Sky-130

AdvancedSynthesisandSTAwithDC

avsdpll28nm

A phase-locked loop or PLL is a control system that generates an output signal whose phase is related to the phase of an input signal. PLLs are widely used for synchronization purposes, including clock generation and distribution inside the SoC’s.

Basys3_FPGA

Basys3 is a FPGA development kit, with a Artix - 7 FPGA

bharath19-gs

Config files for my GitHub profile.

CMOS-Circuit-Design-and-SPICE-Simulation-using-32-28nm

We will be seeing the basic characteristics of NMOS and PMOS of a 28/32 nm technology node.

Cpp

differential_amplifier

synopsys_ICC2flow_130nm

This repo is for synopsys icc2 flow for skywater 130nm PDK

bharath19-gs/6T_SRAM_CELL

SRAM means Static Random Access Memory. The SRAM cell that we considered in this paper was 6T SRAM cell which consists of two crossly coupled inverters and access transistors to read and write the data. In case of the SRAM cell the memory built is being stored around the two cross coupled inverters.

bharath19-gs/AdvancedSynthesisandSTAwithDC

bharath19-gs/synopsys_ICC2flow_130nm

This repo is for synopsys icc2 flow for skywater 130nm PDK

bharath19-gs/CMOS-Circuit-Design-and-SPICE-Simulation-using-32-28nm

We will be seeing the basic characteristics of NMOS and PMOS of a 28/32 nm technology node.

bharath19-gs/AdvancedPhysicalDesign-with-OpenLane-using-Sky-130

bharath19-gs/avsdpll28nm

A phase-locked loop or PLL is a control system that generates an output signal whose phase is related to the phase of an input signal. PLLs are widely used for synchronization purposes, including clock generation and distribution inside the SoC’s.

bharath19-gs/Basys3_FPGA

Basys3 is a FPGA development kit, with a Artix - 7 FPGA

bharath19-gs/bharath19-gs

Config files for my GitHub profile.

bharath19-gs/Cpp

bharath19-gs/differential_amplifier

bharath19-gs/FunctionalNetlistingof_VSDBABYSoC

bharath19-gs/Mixed_signal_triangular_wave_generator

bharath19-gs/My_coding_journey

bharath19-gs/OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

bharath19-gs/Pill_sense

smart pill box (medication purposes)

bharath19-gs/renesas_S7_SK-S7G2_manual

bharath19-gs/UART

bharath19-gs/vsdbabysoc

bharath19-gs/VSDBabySoC_ICC2

bharath19-gs/vsdriscv

bharath19-gs/vsdsquadron

bharath19-gs/XOR-XNOR-Gate