This project is done in the course "Advanced Physical Design using OpenLANE/Sky130" by VLSI System Design Corporation. In this project a complete RTL to GDSII flow for PicoRV32a SoC is executed with Openlane using Skywater130nm PDK. Custom desgined standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified
- Introduction
- Overall Design Flow
- OpenLane Flow
- OpenLane Installation and Environment Setup
- OpenLane Directory Structure
- Working with OpenLane
- Synthesis
- Floorplanning
- Placement
- Cell Design Flow
- Custom Design of SKY130 Standard cell
- Synthesis, Floorplanning with custom standard cell
- Static Timing Analysis
- Floorplanning and Placement
- CTS
- Pre-CTS Timing Analysis in OpenRoad
- PDN
- Routing
- GDSII
- Acknowledgements
- References
With the advent of open-source technologies for Chip development, there were several RTL designs, EDA Tools which were open-sourced. The missing piece in a complete Open source chip development was filled by the SKY130 PDK from Skywater Technologies and Google. There were several EDA Tools, which played specfic roles in the design cycle. There was not a clean design flow and Skywater pdk was compatible with only the industrty tools. OpenLane addressed these issues in providing a completely automated and clean RTL to GDSII flow. OpenLane is not a tool, but a flow which consists of several EDA tools, automation scripts and Skywater-pdks tuned to work specifically with the open-source EDA tools.
For a design Specification an RTL Design is written in HDLs like Verilog /VHDL or RTL Design is generated using Hardware Construction Languages like Chisel or High Level Synthesis using SystemC, MATLAB HDL Coder, Bluespec etc or a modern abstraction level called TL-Verilog (its not a HDL/HLS) , specified by TL-x.org. After this begins the workflow of taking the RTL Netlist into a fabricated IC, which is called as Physical Design Flow.
Physical Design begins with Floor planning - placing the preplaced cells, power planning etc., secondly Placement of Logical Synthesis. Now we do CTS (Clock Tree Synthesis) such there the skew of the clock is the minimum or within the required threshold. After CTS, Routing is done to route all the components placed. Between each and every step that happens in the physical design flow starting from Logic Synthesis to routing, a procedure called "Static Timing Analysis" is done to analyse the design at every step to ensure the actual correctness of the design. To view every stage, Magic is an open source tool to view the layouts. A small netlist can be extracted and a SPICE Simulation can be performed and compared with the Post Layout Simulation using ngspice.
The RTL Level Design is then synthesized using a Logic Synthesizer. We use Yosys which is an Open Source Logic Synthesizer. The RTL Netlist is then converted into a synthesised netlist where there are details about the standard cells and its implementations. Yosys takes the RTL design and timing .libs and verilog models of standard cells and converts into a RTL Netlist. abc does the tehnology mapping to the required skywater-pdk variants
Different strategies can be used to synthesize for the either the least area or the best timing. To analyse this, synthesis exploration utility generates a report showing the effect on delays/timing/area et.,
This is used to suit the design configuration and generate reports with different metrics to select the best. This is also used for regression testing
This is an optional step carried out by Fault. It is used to test the design
This is done by OpenROAD flow. The macros and IPs are placed in the core before proceding further. This is called as pre-placement. Floor planning is done separately for the macros and it is called macro floor planning. They are placed in such a way that they are closer to the inputs/outputs/other macros where more connections are present. Then to prevent the loading effects de-coupling capacitors are placed so that the logic states are well within the noise margin.
When several blocks tap power from a single source, there is a problem of Voltage Droop at the Vdd and Ground Bounce at the Vss which can again push the logic out of the required noise margin into the undefined state. To mitigate this Vdd and Vss are placed as horizontal and vertical strips in the chip so that the blocks can tap power from the nearest source.
There are two types of placement. The other required logic is placed optimally. Placement is of two steps
- Global Placement- finds the optimal position for each cells. These positions are not necessarly correct, cells may overlap
- Detialed Placement - After Global placement is done minimal alterations are done to correct the issues
To ensure minimum skew the Clock is routed optimally through the circuit using different algorithms. This is done in the OpenROAD flow. This is done by TritonCTS.
Long wires acts as antennas and cause accumulation of charges during the fabrication process damaging the transistor. To avoid this bridging is used to pass the wire through different layers or an antenna diode cell is added to leak away the charges
- OpenLane approach - Insert Fake Diode to every cell input during placement. This matches the footprint of the library of the antenna diode. The Antenna Checker is run to check for violations, if there are violations then the fake diode is swapped with a real one.
- OpenROAD approach - In the global route step, the antenna violation is addressed automatically by inserting an antenan diode OpenLane allows the user to chose either of the above approaches
This step is used to implement the interconnect using the different metal layers specified in the PDK. There are two steps
- Global Routing - This is done inside the OpenROAD flow (FastRoute)
- Detailed Routing - This is performed using TritonRoute outside the OpenROAD flow after the global routing. Before performing this step the Logic Equivalence Check is performed by Yosys, since OpenROAD does some optimisations the circuit.
From the .def file, the parasitic extraction is done to generate the .spef file (Standard Prasitic Exchange Format) which produces an accurate analog model of the circuit by including the parasitic effects due to wires, parasitic capacitances, etc.,
At this stage again OpenSTA is used to perform the Static Timing Analysis.
- Design Rule Check (DRC) is performed by Magic
- Layout Versus Schematic (LVS) is performed by Netgen
The routed .def file is used my Magic to generate the GDSII file
Standard Parasitic Exchange Format or SPEF file is generated once place and route is completed. SPEF is used for the delay calculation. It contains R,L,C in the ASCII format. SPEF can be used to perform sign-off post-route STA analysis. The parasitics are extracted into a SPEF file using SPEF Extractor.
GDSII is the file given to the fab. The file is in binary format which represent shapes,labels,text about the layout.
% run_magic
Kunal Ghosh, Co-founder (VSD Corp. Pvt. Ltd)
Nickson P Jose, Teaching Assistant (VSD Corp. Pvt. Ltd)