This paper proposes the implementation of a 6T SRAM cell.A SRAM stores 1 bit of data and also explains its READ and WRITE operation and explains the function of how it stores 1 bit in a cell. This SRAM cell is designed with CMOS logic using the synopsys EDA tool.
The Synopsys Custom Compiler™ design environment is a modern solution for full-custom analog, custom digital, and mixed-signal IC design. As the heart of the Synopsys Custom Design Platform, Custom Compiler provides design entry, simulation management and analysis, and custom layout editing features. It delivers industry-leading productivity, performance, and ease-of-use while remaining easy to adopt for users of legacy tools.
SRAM is Static Random Access Memory, Also known as Read- Write memory, It is a very crucial part of memory in SOCs and ASIC. It constitutes a large percentage of area in the VLSI designs due to the high number of transistors for a single SRAM cell.The need of SRAM is to be stable and robust read/write operation in such a way that it consumes the least power and enhances the on-chip storage capacity.
SRAM takes two design aspects: the power dissipation and propagation delay in reading and writing the value into the SRAM cell. The power dissipated during read and write operation is dynamic power dissipation. It helps to determine the battery life of portable devices. The given circuit demonstrates six transistor SRAM cells, with 4 cross coupled transistors as memory storage cells, and the other two transistors as access transistors.
These access transistors are connected to the bit line and bit line bar that are denoted by “BL & BLB”. And word line here denoted by “WL” is connected to access transistors when the word line is set on, the access transistors can be accessed and similarly when a word line is set off the content of the memory comes set to hold state as the access transistors are turned off, and as a result, the data will remain unchanged in the cell, for the write operation bit line and bit line bar acts as input lines and for reading operation these lines would act as output lines.
Read operation : Both access transistors and are closed while activating the word line. When, cell(crossed inverters) comes to state 1 then signal flows in high amount on bitline(BL) and other side signal flows in low amount on bitline bar(BLB). Opposite is true when cell goes to state 0. Finally both BL and BLB get complement of each other’s. Sense/write, which are connected in the rear side of two bit line, they monitor their states and finally convert into output respectively.
write operation : In the write operation, Sense/Write circuit allows to drive bit lines BL and it complement BLB, and then it provides accurate values on bit line BLB and BLB as well as go to activate word line(the data is written into the cell once the word line(WL) is activated and deactivated in a span of time).
These operations can be observed in the below waveforms
The basic 6T SRAM cell basic design.
The symbol of 6T SRAM cell with analysis.
-
With BL starting with '0' and BLB starting with '1', we can observe the basic working of the SRAM cell with respect to time. the Q value changing only when the Write line is active, and rest of the time cell is known to be at static or hold state.
-
With BL starting with '1' and BLB starting with '0'.
- read operation : we can see the reading being done by the bit line(BL) and bit line bar (BLB), as here while simulating we are giving a initial value to Q, and observing it at BL, we need use a precharged capacitor to do the read operation on the SRAM cell.
- write operation : we can see the writing being done as soon as the write line gets activated the bitline bar(BLB) acts as a input line which inturn causes the value in teh cell to change to the value that is on the input line.
.global gnd! vdd!
********************************************************************************
* Library : GSB_6T_SRAM
* Cell : 6T_SRAM_CELL
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt _6t_sram_cell bl blb gnd_1 q qb vdd wl vt_bulk_n_gnd! vt_bulk_p_vdd!
xm13 qb q gnd_1 vt_bulk_n_gnd! n25 w=0.36u l=0.26u nf=1 m=1
xm14 q qb gnd_1 vt_bulk_n_gnd! n25 w=0.36u l=0.26u nf=1 m=1
xm15 q wl bl vt_bulk_n_gnd! n25 w=0.36u l=0.26u nf=1 m=1
xm16 blb wl qb vt_bulk_n_gnd! n25 w=0.36u l=0.26u nf=1 m=1
xm11 qb q vdd vt_bulk_p_vdd! p25 w=0.36u l=0.26u nf=1 m=1
xm12 q qb vdd vt_bulk_p_vdd! p25 w=0.36u l=0.26u nf=1 m=1
.ends _6t_sram_cell
********************************************************************************
* Library : GSB_6T_SRAM
* Cell : 6T_SRAM_CELL_tb
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
xi0 net12 net14 gnd! net1 net2 net9 net10 gnd! vdd! _6t_sram_cell
v1 net9 gnd! dc=1
v9 net14 gnd! dc=0 pulse ( 0 1 0.1n 0.1n 0.1n 5n 10n )
v8 net12 gnd! dc=0 pulse ( 1 0 0.1n 0.1n 0.1n 5n 10n )
v2 net10 gnd! dc=0 pulse ( 1 0 0.1n 0.1n 0.1n 20n 40n )
.tran '10n' '200n' name=tran
.option primesim_remove_probe_prefix = 0
.probe v(*) i(*) level=1
.probe tran v(net1) v(net10) v(net12) v(net14)
.temp 25
.option primesim_output=wdf
.option parhier = LOCAL
- Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - kunalpghosh@gmail.com
- Chinmay panda, IIT Hyderabad
- Sameer Durgoji, NIT Karnataka
- Synopsys Team/Company
[1] Design and performance analysis of 6T SRAM cell on different CMOS technologies with stability characterization Shikha Saun1 and Hemant Kumar1
[2] SRAM operation, https://www.iue.tuwien.ac.at/phd/entner/node34.html