A phase-locked loop or PLL is a control system that generates an output signal whose phase is related to the phase of an input signal.
PLLs are widely used for synchronization purposes, including clock generation and distribution inside the SoC’s.
We will be building the PLL using 28nm
technology node.
- 28/32nm PDK
- Tools Overview
- PLL introduction
- Circuit Details
- Circuit Design
- Simulations
- References
- Acknowlegements
32-nanometer refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technology level. The 28-nanometer node was an intermediate half-node die shrink based on the 32-nanometer process.
So for the design of the PLL we will be using the 28/32nm PDK file.
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PrimeSim HSPICE PrimeSim HSPICE is the accurate circuit simulator and offers foundries-certified MOS device models with state-of-theart simulation and analysis algorithms. It is used for building digital MOSFET circuits using 28nm technology.
Phase locked loops mainly consist of the following 4 components
- Charge pump(CP)
- Phase Frequency Detector(PFD)
- Voltage Controlled Oscillator(VCO)
- Loop Filter
- Frequency Divider(FD)
A phase-locked loop or PLL is a closed loop feedback circuit comprises of four main blocks phase frequency detector (PFD), charge pump (CP), low pass filter (LPF) and voltage-controlled oscillator (VCO) PLL as shown in Fig.1. These blocks are connected to form a closed loop feedback network so as to synchronize the output with the input in both phase and frequency. And this loop continues to run until PLL locked condition is achieved i.e., either zero or constant phase difference between the reference input and the feedback pulse from the output of PLL. PLL is castoff as on chip clock generator, frequency synthesizer and clock and data recovery system in radio, computers and telecommunication system. In general, as technology scale down a PLL with wide tuning range, low jitter, and PLL operating at high frequencies are preferred.
The specifications for PLL to be designed are:
Corner - 'TT' (Typical-Typical/Normal-Normal)\n
Supply Voltage - 1.5V
Room Temperature - 27
VCO mode and PLL mode
Input Fmin=5Mhz; Fmax=12.5Mhz
Multiplier - 8x
Jitter(RMS) < ~20ns
Duty Cycle - 50%
The above image shows the basic PLL design with all the internal blocks integrated.
Let us discuss about each block in the PLL circuit design.
- Phase Frequency Detector(PFD)
The phase frequency detector(PFD) is responsible for comparing 2 signals(the reference signal and the output signal).So, from the comparing of the 2 signals we get to know that which signal is leading/lagging comnmpared to the other,The ouput of PFD is in digital form.
The PFD schematic can be observed below with the symbol generated using the Tool for the Pre-layout simulations.
- Charge pump(CP)
The CP converts the digital output from PFD to an analog signal . This analog signal is what would control the Voltage Controlled Oscillator(VCO). The analog ouput from CP is passed through a low pass filter before connecting to the VCO. This low pass filter can help smoothen the signal in addition to stabilizing the feedback loop.
The CP schematic can be observed below with the symbol generated using the Tool for the Pre-layout simulations.
- Loop Filter
A low pass filter is used to remove out the noise from a signal, noise are high frequency signals. In the case of our PLL it is used to smoothen out the signal for the Voltage Controlled Oscillator(VCO).
- Voltage Controlled Oscillator(VCO)
Voltage controlled oscillators are the actual parts which produces alternating digital clock signal. The frequency of this clock signal can be controlled by input voltage, hence the name.
The PFD schematic can be observed below with the symbol generated using the Tool for the Pre-layout simulations.
- Frequency Divider(FD)
A PLL with a frequency divider on its feedback loop is called a clock multiplier PLL. Such a PLL can make clock signals which are multiples of the reference signals.
First lets start with the outputs of the VCO(Voltage controlled Oscillator)
going ahead with CP(charge pump)
case 1: with the UP input acitvated.
case 2: with the DOWN input activated.
Next is the FD(Frequency Divider)(just one stage)
Finally the PFD(Phase Frequency Detector) Block
The final Output of the PLL is as below with all blocks integrated.
[1] PLL Design using 130nm PDK
[2] Phase locked loop
Kunal Ghosh, Co-founder , VSD Corp. Pvt. Ltd. - kunalpghosh@gmail.com
Muthukrishnan Chinnasamy , CEO of SFAL
Montu Makadia, SFAL
Lakshmi S, Instructor - 8x PLL Clock Multiplier IP