Vaknafusu's Stars
walkerning/aw_nas
aw_nas: A Modularized and Extensible NAS Framework
Aayush-Ankit/puma-simulator
[ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and runs ML models compiled using the puma compiler.
Pitt-JonesLab/DWMsimulator
pycharm DWM simulator
HiggsBose/ResNet20-with-LSQ-quantization
A ResNet20 with LSQ quantization for in-memory computing based on RRAM
YulhwaKim/RRAMScalable_BNN
Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators
coreylammie/MemTorch
A Simulation Framework for Memristive Deep Learning Systems
lvyufeng/mistral-mindspore
zjysteven/bitslice_sparsity
Codes for our paper "Exploring Bit-Slice Sparsity in Deep Neural Networks for Efficient ReRAM-Based Deployment" [NeurIPS'19 EMC2 workshop].
abdelazeem201/ASIC-Design-Roadmap
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
I-Doctor/RTL_library_of_basic_hardware_units
Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and support the hardware design tradeoff.
thu-nics/MNSIM-2.0
A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems
mayshin10/CNN-Accelerator
Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.
lirui-shanghaitech/CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
Ams0x57/Digital_Adders_Verilog
32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their internal components in Verilog
arkarthi/Generic_FP_Multiplier
Generic Floating Point Multiplier
ShannonM-code/floating-point-multiplication
Floating point multiplier with booth encoded Wallace tree multiplier
suoglu/Fixed-Floating-Point-Adder-Multiplier
16-bit Adder Multiplier hardware on Digilent Basys 3
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
That is a design a floating point multiplier based in the ieee standard 764 using vhdl and it has been implemented in the FPGA Cyclone II
MundhadaNidhi/16-Bit-Vedic-Multiplier-using-FPGA
In this project, the design of 16 x 16 Vedic Multiplier Using Urdhva Tiryagbhyam Sutra is implemented. Also, the comparison of maximum combinational path latency, chip area consumption, and total on-chip power of an 8- bit Vedic multiplier using Urdhva Tiryagbhyam sutra, an 8-bit Wallace tree multiplier, and an 8-bit Array Multiplier written in Verilog is done.
Janya21/Multipliers_Verilog
This repository contains verilog programs for Wallace and Vedic multipliers.
rcetin/booth_wallace_multiplier
Booth encoded Wallace tree multiplier
pareddy113/Design-of-various-multiplier-Array-Booth-Wallace-
ZhongYi-LinuxDriverDev/CS-EmbeddedLinux-Book
嵌入式,计算机常用电子书籍整理,并且附带下载链接,涵盖:ARM体系与架构,C/C++语言,汇编语言,操作系统,计算机网络,计算组成原理,Linux驱动,Linux内核,单片机开发,程序员认知成长,笔试面试技巧等书籍。长期更新中,欢迎star~
tahhan/imageProc
A simple Image Processing application with GUI using Python and PyQt4
imdeep2905/Notch-Filter-for-Image-Processing
Implemented Ideal, ButterWorth and Gaussian Notch Filter for Image processing in python (with GUI).
dsoellinger/blind_image_quality_toolbox
Collection of Blind Image Quality Metrics in Matlab
igorcmoura/inpaint-object-remover
Python implementation of "Region Filling and Object Removal" by A. Criminisi et al.
Shubham-Sahoo/Image_inpainting
"Region Filling and Object Removal by Exemplar-Based Image Inpainting" by Criminisi et al
cantarinigiorgio/Image-Inpainting
This project is an implementation of "Region Filling and Object Removal by Exemplar-Based Image Inpainting" by A.Criminisi
ikuwow/inpainting_criminisi2004
MATLAB Implementation of inpainting Algorithm by A. Criminisi (2004)