Pinned Repositories
eUVM_worskshop_avst_adder
Example setup for UVM driven Icarus Verilog Simulation
Fork-PROBE-3.0-v.0
Inventory-management-system
Memory-Design-And-Testing
The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso
SCL-Design-Workshop-24
Welcome to the Standard Cell Design Workshop repository. Here, you'll find all the necessary files and resources for a hands-on learning experience.
VardhanSuroshi
Config files for my GitHub profile.
Vedic-Multiplier-Efabless-Tapeout
Vedic-Multiplier-From-RTL2GDS
GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
VLSI-ASIC-Design-Flow
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
VLSI-Physical-Design-Flow
This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of OpenLANE. This repo is the continuity of VLSI ASIC Design Flow
VardhanSuroshi's Repositories
VardhanSuroshi/Memory-Design-And-Testing
The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso
VardhanSuroshi/VLSI-ASIC-Design-Flow
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
VardhanSuroshi/SCL-Design-Workshop-24
Welcome to the Standard Cell Design Workshop repository. Here, you'll find all the necessary files and resources for a hands-on learning experience.
VardhanSuroshi/VLSI-Physical-Design-Flow
This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of OpenLANE. This repo is the continuity of VLSI ASIC Design Flow
VardhanSuroshi/eUVM_worskshop_avst_adder
Example setup for UVM driven Icarus Verilog Simulation
VardhanSuroshi/Fork-PROBE-3.0-v.0
VardhanSuroshi/Inventory-management-system
VardhanSuroshi/VardhanSuroshi
Config files for my GitHub profile.
VardhanSuroshi/Vedic-Multiplier-Efabless-Tapeout
VardhanSuroshi/Vedic-Multiplier-From-RTL2GDS
GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA