VesselLee's Stars
plctlab/PLCT-Weekly
软件所PLCT实验室在开源领域的不定期简报
plctlab/llvm-project
PLCT实验室的 RISC-V V Spec 实现,基于llvm/llvm-project,rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
Starrynightzyq/soNN
A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
lirui-shanghaitech/CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
schoeberl/chisel-examples
Chisel examples and code snippets
chipsalliance/firrtl
Flexible Intermediate Representation for RTL
chipsalliance/rocket-chip
Rocket Chip Generator
ucb-bar/chisel-tutorial
chisel tutorial exercises and answers
schoeberl/chisel-book
Digital Design with Chisel
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
papcjy/mnist_fpga
using xilinx xc6slx45 to implement mnist net
kmod/bitcoin_mining
Simple test fpga bitcoin miner
LeiWang1999/ZYNQ-NVDLA
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
soDLA-publishment/soDLA
Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
mflowgen/freepdk-45nm
ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
freechipsproject/chisel-bootcamp
Generator Bootcamp Material: Learn Chisel the Right Way
celerity/celerity-runtime
High-level C++ for Accelerator Clusters
obilaniu/MVU
Neural Network accelerator powered by MVUs and RISC-V.
NekoSilverFox/Assembly
⚡ 亲手编写实现基于王爽老师《汇编语言》的300个汇编程序例程 | Implementation of 300 assembly program examples based on "Assembly Language"
WangXuan95/USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。
riscv-mcu/e203_hbirdv2
The Ultra-Low Power RISC-V Core
riscvarchive/educational-materials
Educational materials for RISC-V
drichmond/RISC-V-On-PYNQ
RISC-V Integration for PYNQ
cksystemsteaching/selfie
An educational software system of a tiny self-compiling C compiler, a tiny self-executing RISC-V emulator, and a tiny self-hosting RISC-V hypervisor.
SpinalHDL/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
SymbioticEDA/riscv-formal
RISC-V Formal Verification Framework
ucb-bar/riscv-sodor
educational microarchitectures for risc-v isa
riscv/riscv-v-spec
Working draft of the proposed RISC-V V vector extension
riscvarchive/riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
riscv/riscv-opcodes
RISC-V Opcodes