XUANTIE-RV/wujian100_open
IC design and development should be faster,simpler and more reliable
VerilogMIT
Issues
- 0
钉钉讨论群二维码过期
#62 opened - 0
Readme information update
#61 opened - 0
关于ip核配置
#60 opened - 1
synthesis failed
#59 opened - 1
没有官方的调试器能用jtag调试器替代吗
#58 opened - 0
发现文档有个地方有错
#57 opened - 1
GPIO cannot clear interrupt
#56 opened - 1
- 6
請問CDK能支援其他openOCD相容的JTAG嗎?
#54 opened - 1
Core is not modifiable
#53 opened - 1
钉钉群二维码失效了,可以更新一下吗,有很多问题想问。
#52 opened - 1
几个问题,最后一个问题比较急,谢谢
#51 opened - 2
- 1
为什么我用vivado2019.1综合后时序不对
#49 opened - 1
平头哥适配过的工具链有开源链接么
#48 opened - 1
请问钉钉群现在是不能加入了吗
#47 opened - 5
request for spec of hardware side
#44 opened - 1
开发文档的一些建议
#43 opened - 2
为什么板子和群里的原理图对应不起来啊
#41 opened - 2
- 0
- 1
- 0
verilog的命名规则、缩写规范
#36 opened - 0
语法错误
#35 opened - 9
编译case异常。
#34 opened - 2
建议支持Yosys
#32 opened - 5
现在申请开发板试用,能用多长时间?
#31 opened - 9
FPGA实现为什么要用synplify综合,全vivado流程有什么问题吗?
#27 opened - 1
About Driver of CK-Linker for WIN10
#26 opened - 3
请问应用程序如何下载到MCU里面?是通过JTAG接口吗
#24 opened - 3
请问平头哥的FPGA开发板在哪里可以买得到?
#23 opened - 3
Failed to load program while simulating
#21 opened - 3
请问一下有MCU的基本信息吗
#20 opened - 0
- 0
- 2
Write_bitstream failed!
#15 opened - 1
wechat pic is not working
#13 opened - 1
哪里能看到设计文档?
#12 opened - 6
突然想转行
#11 opened - 1
DEBUG 调试工具
#10 opened - 0
No comments?
#9 opened - 2
how to download tool-chain ?
#8 opened - 2
about annotation
#7 opened - 4
Verilog 语言文件只有顶层文件开源,内部实现不开源么~
#6 opened - 10
- 7
建议支持 iverilog + gtkwave
#4 opened